CD4027BCN Datasheet, PDF (4/6 Pages) Fairchild Semiconductor – Dual J-K Master/Slave Flip-Flop with Set and Reset

AC Electrical Characteristics (Note 8)
T_A = 25°C, C_L = 50 pF, t_rCL = t_fCL = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL or t_PLH
t_PHL or t_PLH
t_PHL or t_PLH
t_S
Propagation Delay Time
from Clock to Q or Q
Propagation Delay Time
from Set to Q or Reset to Q
Propagation Delay Time
from Set to Q or
Reset to Q
Minimum Data Setup Time
t_THL or t_TLH
Transition Time
f_CL
t_rCL or t_fCL
t_W
t_WH
C_IN
C_PD
Maximum Clock Frequency
(Toggle Mode)
Maximum Clock Rise
and Fall Time
Minimum Clock Pulse
Width (t_WH = t_WL)
Minimum Set and
Reset Pulse Width
Average Input Capacitance
Power Dissipation Capacity
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
Any Input
Per Flip-Flop
(Note 9)
200
400
80
160
ns
65
130
170
340
70
140
ns
55
110
110
220
50
100
ns
40
80
135
270
55
110
ns
45
90
100
200
50
100
ns
40
80
2.5
5
6.2
12.5
MHz
7.6
15.5
15
10
µs
5
100
200
40
80
ns
32
65
80
160
30
60
ns
25
50
5
7.5
pF
35
pF
Note 8: AC Parameters are guaranteed by DC correlated testing.
Note 9: C_PD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application
note, AN-90.
Typical Applications
Ripple Binary Counters
Shift Registers
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