CD4027BCN Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Dual J-K Master/Slave Flip-Flop with Set and Reset

October 1987
Revised January 2004
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to V_DD and V_SS.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 V_DD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s Low power: 50 nW (typ.)
s Medium speed operation: 12 MHz (typ.) with 10V
supply
Ordering Code:
Order Number
CD4027BCM
CD4027BCN
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
Top View
Truth Table
Inputs t_n−1
(Note 1)
Outputs t_n
(Note 2)
CL J K S R Q Q
Q
^{(Note 3)}
I
X
O
X
X
X
O
X
I
X
O
O
O
O
O
O
O
O
O
O
O
I
O
I
X
I
O
I
O
O
I
O
I
(No Change)
X
XX I OX I
O
X
XXO I X O
I
X
XX I I X I
I
I = HIGH Level
O = LOW Level
X = Don’t Care
 = LOW-to-HIGH
 = HIGH-to-LOW
Note 1: t_n−1 refers to the time interval prior to the positive clock pulse
transition
Note 2: t_n refers to the time intervals after the positive clock pulse
transition
Note 3: Level Change
© 2004 Fairchild Semiconductor Corporation DS005958
www.fairchildsemi.com