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74ABT16541 Datasheet, PDF (4/8 Pages) NXP Semiconductors – 16-bit buffer/line driver 3-State
DC Electrical Characteristics (Continued)
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VILD
Maximum LOW Level Dynamic Input Voltage
1.2
0.8
V
5.0 TA 25qC (Note 5)
Note 3: Guaranteed but not tested.
Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n  1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
tPLH
Propagation
tPHL
Delay Data to Outputs
tPZH
Output Enable
tPZL
Time
tPHZ
Output Disable
tPLZ
Time
TA 25qC
VCC 5V
CL 50 pF
Min
Typ
Max
1.0
2.3
3.4
1.0
2.7
3.9
1.5
3.5
5.2
1.5
3.5
6.0
1.0
4.2
5.1
1.0
3.2
5.1
TA 40qC to 85qC
VCC 4.5V–5.5V
CL 50 pF
Min
Max
1.0
3.4
1.0
3.9
1.5
5.2
1.5
6.0
1.0
5.1
1.0
5.1
Units
ns
ns
ns
Extended AC Electrical Characteristics
40qC to 85qC
TA 40qC to 85qC TA 40qC to 85qC
VCC 4.5V–5.5V
VCC 4.5V–5.5V
VCC 4.5V–5.5V
Symbol
Parameter
CL 50 pF
16 Outputs Switching
CL 250 pF
1 Output Switching
CL 250 pF
Units
16 Outputs Switching
(Note 7)
(Note 8)
(Note 9)
Min
Typ
Max
Min
Max
Min
Max
fTOGGLE
Maximum Toggle Frequency
100
tPLH
Propagation Delay
1.5
5.0
1.5
6.0
2.5
8.0
tPHL
Data to Outputs
1.5
5.3
1.5
6.0
2.5
8.0
tPZH
Output Enable
1.5
6.5
2.5
7.8
2.5
9.5
tPZL
Time
1.5
6.5
2.5
7.8
2.5
8.5
tPHZ
Output Disable
1.0
6.7
(Note 10)
(Note 10)
tPLZ
Time
1.0
6.7
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
MHz
ns
ns
ns
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: The 3-STATE delay times are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet.
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