FDMF5821DCCT-ND Datasheet, PDF (3/25 Pages) Fairchild Semiconductor – FDMF5821DC . Smart Power Stage (SPS) Module with Integrated Temperature Monitor

Pin Configuration
Figure 3. Pin Configuration - Top View and Transparent View
Pin Definitions
Pin #
1
2
3
4, 32
Name
PWM
ZCD#
VCC
AGND
5
BOOT
6
7
8~11
12~15, 28
NC
PHASE
VIN
PGND
16~26
SW
27, 33
29
30
GL
PVCC
TMON
31
EN /
FAULT#
Notes:
1. LS = Low Side.
2. HS = High Side.
Description
PWM input to the gate driver IC
Enable input for the ZCD (Auto DCM) comparator
Power supply input for all analog control functions; this is the “quiet” V_CC
Analog ground for analog portions of the IC and for substrate
Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies
the charge to turn on the N-channel high-side MOSFET
No connect
Return connection for the boot capacitor, internally tied to SW node
Power input for the power stage
Power return for the power stage
Switching node junction between high-side and low-side MOSFETs; also input to the gate
driver SW node comparator and input into the ZCD comparator
Gate Low, Low-side MOSFET gate monitor
Power supply input for LS⁽¹⁾ gate driver and boot diode
Temperature monitoring & reporting / programmable thermal shutdown pin
Dual-functionality: enable input to the gate driver IC; FAULT# - internal pull-down
physically pulls this pin LOW upon detection of fault condition (HS⁽²⁾ MOSFET short or
TMON signal exceeding 1.5 V)
© 2013 Fairchild Semiconductor Corporation
FDMF5821DC • Rev. 1.0.1
3
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