FAN3223 Datasheet, PDF (3/24 Pages) Fairchild Semiconductor – Dual 4A High-Speed, Low-Side Gate Drivers

FAN3223
FAN3224
Figure 4. Pin Assignments (Repeated)
FAN3225
Pin Definitions
Name
Pin Description
ENA
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND Ground. Common ground reference for input and output circuits.
INA Input to Channel A.
INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA- Inverting Input to Channel A. Connect to GND to enable output.
INB Input to Channel B.
INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB- Inverting Input to Channel B. Connect to GND to enable output.
OUTA
OUTB
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
OUTB _{above UVLO threshold.}
P1
Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
VDD Supply Voltage. Provides power to the IC.
Output Logic
FAN3223 (x=A or B)
FAN3224 (x=A or B)
ENx
INx
OUTx
ENx
INx
0
0
0
0
1⁽⁷⁾
0
1⁽⁷⁾
0
1
1⁽⁷⁾
1⁽⁷⁾
0
0
0⁽⁷⁾
0
1
1⁽⁷⁾
0⁽⁷⁾
1⁽⁷⁾
1
Note:
7. Default input signal if no external connection is made.
OUTx
0
0
0
1
© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
3
FAN3225 (x=A or B)
INx+
0⁽⁷⁾
0⁽⁷⁾
1
1
INx−
0
1⁽⁷⁾
0
1⁽⁷⁾
OUTx
0
0
1
0
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