74F646 Datasheet, PDF (3/9 Pages) NXP Semiconductors – Octal transceiver/register, non-inverting 3-State

Unit Loading/Fan Out
Pin Names
A₀–A₇
B₀–B₇
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
U.L.
HIGH/LOW
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input I_IH/I_IL
Output I_OH/I_OL
70 µA/−650 µA
−12 mA/64 mA (48 mA)
70 µA/−650 µA
−12 mA/64 mA (48 mA)
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Function Table
Inputs
Data I/O (Note 1)
G DIR CPAB CPBA SAB SBA A₀–A₇ B₀–B₇
Function
H
H
H
X
X
X
H or L H or L
X
 X
X
X
X
X
Isolation
X
Input Input Clock A_n Data into A Register
X
Clock B_n Data into B Register
L
L
H
H
^X
X
X
L
L
X
A_n to B_n—Real Time (Transparent Mode)
X
Input Output Clock A_n Data into A Register
L
L
 ^{H H or L X}
H
X
H
H
X
X
A Register to B_n (Stored Mode)
Clock A_n Data into A Register and Output to B_n
L
L
L
L
X
X
^X
X
X
L
B_n to A_n—Real Time (Transparent Mode)
L Output Input Clock B_n Data into B Register
L
L
L
L
 ^{X H or L X}
X
X
H
H
B Register to A_n (Stored Mode)
Clock B_n Data into B Register and Output to A_n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Irrelevant
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
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