ACE1202 Datasheet, PDF (26/39 Pages) Fairchild Semiconductor – Arithmetic Controller Engine (ACEx™) for Low Power Applications

After the HBC has started, software must then poll the OCFLAG
for a high pulse and restore the DAT0 register and the START
signal to continue with the next data transmission.
LOOP_HI:
IFBIT OCFLAG, HBCNTRL ; Wait for OCFLAG = 1
JP NXT_FRAME
JP LOOP_HI
NXT_FRAME:
LD DAT0, #092H
SBIT START, HBCNTRL
; DAT0 = 0x92
; START / STOP = 1
If software is to proceed with another data transmission, the
OCFLAG must be zero before polling for the next OCFLAG high
pulse. However, since the specification in the example requires no
other data transmission software can proceed as desired.
LOOP_LO:
IFBIT OCFLAG, HBCNTRL ; Wait for OCFLAG = 0
JP LOOP_LO
Etc.
; Program proceeds as desired
Figure 21: Hardware Bit-Coder (HBC) Block Diagram
IR/RF
CLOCK
CPU
CLOCK
Fixed
Clock Divider
by 4
PSCALE
8
[PSCALE]
RFCLK
StopShift ^HPATTERN
b7
RFCLK
StopShift
LPATTERN
b7
A
Y
G2
B
G5
IOSEL
HBCNTRL[6]
Down
Counter
3
Y
A
B
ShiftCLK
DAT0 ^b7
NoShift OCFLAG
3
FRAME[2:0]
[HBCNTRL]
OCFLAG
HBCNTRL[7]
Sync
LOGIC
START/STOP
HBCNTRL[5]
TXBUSY
HBCNTRL[4]
3
3
BPH[2:0]
[BPSEL]
BPL[2:0]
[BPSEL]
Figure 22: Bit Period Configuration (BPSEL) Register
Bit 7
0
Bit 6
0
Bit 5
Bit 4
BPL[2:0]
Bit 3
Bit 2
Bit 1
BPH[2:0]
Bit 0
Figure 23: HBC Control (HBCNTRL) Register
Bit 7
Bit 6
Bit 5
Bit 4
OCFLAG
IOSEL
START/STOP TXBUSY
Bit 3
0
Bit 2
Bit 1
FRAME[2:0]
Bit 0
26
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com