ACE1202 Datasheet, PDF (12/39 Pages) Fairchild Semiconductor – Arithmetic Controller Engine (ACEx™) for Low Power Applications

4.0 Arithmetic Controller Core
The ACEx microcontroller core is specifically designed for low
cost applications involving bit manipulation, shifting and block
encryption.It is based on a modified Harvard architecture meaning
peripheral, I/O, and RAM locations are addressed separately from
instruction data.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This allows
the X-pointer (12-bits) to point to any memory location in either
segment of the memory map. This modification improves the
overall code efficiency of the ACEx microcontroller and takes
advantage of the flexibility found on Von Neumann style ma-
chines.
4.1 CPU Registers
The ACEx microcontroller has five general-purpose registers.
These registers are the Accumulator (A), X-Pointer (X), Program
Counter (PC), Stack Pointer (SP), and Status Register (SR). The
X, SP, and SR registers are all memory-mapped.
Figure 12: Programming Model
A
7
0 8-bit accumulator register
X 11
0 12-bit X pointer register
PC 10
0 11-bit program counter
SP
3 0 4-bit stack pointer
SR
R 0 0 G Z C H N 8-bit status register
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
12
ACE1202 Product Family Rev. B.1
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