ACE1501 Datasheet, PDF (25/33 Pages) Fairchild Semiconductor – ACE1501 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications

11.1 Brown-out Reset
The Brown-out Reset (BOR) function is used to hold the device
in reset when Vcc drops below a fixed threshold (1.83V.) While
in reset, the device is held in its initial condition until Vcc rises
above the threshold value. Shortly after Vcc rises above the
threshold value, an internal reset sequence is started. After the
reset sequence, the core fetches the first instruction and starts
normal operation.
The BOR should be used in situations when Vcc rises and falls
slowly and in situations when Vcc does not fall to zero before
rising back to operating range. The Brown-out Reset can be
thought of as a supplement function to the Power-on Reset if
Vcc does not fall below ~1.5V. The Power-on Reset circuit works
best when Vcc starts from zero and rises sharply. In applica-
tions where Vcc is not constant, the BOR will give added device
stability.
The BOR circuit must be enabled through the BOR enable bit
(BOREN) in the initialization register. The BOREN bit can only
be set while the device is in programming mode. Once set, the
BOR will always be powered-up enabled. Software cannot dis-
able the BOR. The BOR can only be disabled in programming
mode by resetting the BOREN bit as long as the global write
protect (WDIS) feature is not enabled.
Figure 33. BOR and POR Circuit Relationship Diagram
Vcc (Pin 8)
BOR
output
VCC
1.75
0
VCC
0
VCC
Time
BOR Output
POR
output
VCC
5.0V
(Pin 7)
1.8V
0
VCC
POR
output ₀
Reset
circuit
A output
Global Reset
to Logic
External
Reset
Pin
(14-Pin Only)
POR Output
Pulse
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all
controller logic. The Global
Reset will go high and stay high
for around 1us.
11.2 Low Battery Detect
The Low Battery Detect (LBD) circuit allows software to monitor
the Vcc level at the lower voltage ranges. LBD has a 32-level
software programmable voltage reference threshold that can be
changed on the fly. Once Vcc falls below the selected threshold,
the LBD flag in the LBD control register is set. The LBD flag will
hold its value until Vcc rises above the threshold. (See Table 15)
The LBD bit is read only. If LBD is 0, it indicates that the Vcc
level is higher than the selected threshold. If LBD is 1, it indi-
cates that the Vcc level is below the selected threshold. The
threshold level can be adjusted up to eight levels using the three
trim bits (BL[4:0]) of the LBD control register. The LBD flag does
not cause any hardware actions or an interruption of the proces-
sor. It is for software monitoring only.
The VSEL bit of the LBD control register can be used to select
an external voltage source rather than Vcc. If VSEL is 1, the
voltage source for the LBD comparator will be an input voltage
provided through G4. If VSEL is 0, the voltage source will be
Vcc.
The LBD circuit must be enabled through the LBD enable bit
(LBDEN) in the initialization register. The LBDEN bit can only be
set while the device is in programming mode. Once set, the LBD
will always be powered-up enabled. Software cannot disable the
LBD. The LBD can only be disabled in programming mode by
resetting the LBDEN bit as long as the global write protect
(WDIS) feature is not enabled.
The LBD circuit is disabled during HALT/IDLE mode. After exit-
ing HALT/IDLE, software must wait at lease 10 µs before read-
ing the LBD bit to ensure that the internal circuit has stabilized.
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ACE1501 Product Family Rev. 1.1
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