ACE1501 Datasheet, PDF (16/33 Pages) Fairchild Semiconductor – ACE1501 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications

5. Write the appropriate control value to the T1CNTRL register
to select External Event Counter mode, to clock every falling
edge, to set the enable bit, to clear the pending flag, and to
start the counter. (See Table 11 and Table 12 )
- LD T1CNTRL, #34H (#00h) ;Setting the T1C0 bit starts
the timer
6. When the counter underflows, the interrupt service routine
must clear the T1PND flag and take whatever action is
required once the number of events occurs. If the software
wishes to merely count the number of events and the antici-
pated number may exceed 65,536, the interrupt service
routine should record the number of underflows by incre-
menting a counter in memory. Software can then calculate
the correct event count.
- RBIT T1PND, T1CNTRL ; T1PND equals 3
Figure 16. External Event Counter Mode
Underflow
Interrupt
16-bit Auto-Reload
Register (T1RA)
16-bit Counter (TMR1)
Data
Bus
T1
Edge Selector
Logic
4.4 Mode 3: Input Capture Mode
In the Input Capture mode, the timer is used to measure
elapsed time between edges of an input signal. Once the timer
is configured for this mode, the timer starts counting down
immediately at the instruction clock rate. The Timer 1 will then
transfer the current value of the TMR1 register into the T1RA
register as soon as the selected edge of T1 is sensed. The input
signal on T1 must have a pulse width equal to or greater than
one instruction clock cycle. At every T1RA capture, software
can then store the values into RAM to calculate the elapsed
time between edges on T1. At any given time (with proper con-
sideration of the state of T1) the timer can be configured to cap-
ture on positive-going or negative-going edges. A block diagram
of the timer’s Input Capture mode of operation is shown in Fig-
ure 17.
The timer has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable)
bit of the SR is set. The Input Capture mode contains two inter-
rupt pending flags 1) the TMR1 register capture in T1RA
(T1PND) and 2) timer underflow (T1C0). If interrupts are
enabled, the timer will generate an interrupt each time a pend-
ing flag is set (provided that the pending flag was previously
cleared.) The interrupt service routine is responsible for proper
handling of the T1PND flag, T1C0 flag, and the T1EN bit.
For this operating mode, the T1C0 control bit serves as the
timer underflow interrupt pending flag. The Timer 1 interrupt ser-
vice routine must read both the T1PND and T1C0 flags to deter-
mine the cause of the interrupt. A set T1C0 flag means that a
timer underflow occurred whereas a set T1PND flag means that
a capture occurred in T1RA. It is possible that both flags will be
found set, meaning that both events occurred at the same time.
The interrupt service routine should take this possibility into
consideration.
Because the T1C0 bit is used as the underflow interrupt pend-
ing flag, it is not available for use as a start/stop bit as in the
other modes.
The TMR1 register counts down continuously at the instruction
clock rate starting from the time that the input capture mode is
selected. (See Table 11 and Table 12) To stop the timer from
running, you must change the mode to an alternate mode
(PWM or External Event Counter) while resetting the T1C0 bit.
The input pins can be independently configured to sense posi-
tive-going or negative-going transitions. The edge sensitivity of
pin T1 is controlled by bit T1C1 as indicated in Table 12.
The edge sensitivity of a pin can be changed without leaving the
input capture mode even while the timer is running. This feature
allows you to measure the width of a pulse received on an input
pin.
For example, the T1 pin can be programmed to be sensitive to a
positive-going edge. When the positive edge is sensed, the
TMR1 register contents is transferred to the T1RA register and
a Timer 1 interrupt is generated. The Timer 1 interrupt service
routine records the contents of the T1RA register, changes the
edge sensitivity from positive to negative-going edge, and
clears the T1PND flag. When the negative-going edge is sensed
another Timer 1 interrupt is generated. The interrupt service
routine reads the T1RA register again. The difference between
the previous reading and the current reading reflects the
elapsed time between the positive edge and negative edge of
the T1 input signal i.e. the width of the positive-going pulse.
Remember that the Timer1 interrupt service routine must test
the T1C0 and T1PND flags to determine the cause of the inter-
rupt. If the T1C0 flag caused the interrupt, the interrupt service
routine should record the occurrence of an underflow by incre-
menting a counter in memory or by some other means. The
software that calculates the elapsed time between captures
should take into account the number of underflow that occurred
when making its calculation.
The following steps show how to properly configure Timer 1 to
operate in the Input Capture mode.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
- RBIT 2, PORTGC
; Configure G2 as an input
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Enable the global interrupt enable bit.
- SBIT 4, STATUS
4. With the timer stopped, load the initial time into the TMR1
register (typically the value is 0xFFFF.)
- LD TMR1LO, #0FFH
- LD TMR1HI, #0FFH
5. Write the appropriate control value to the T1CNTRL register
to select Input Capture mode, to sense the appropriate
edge, to set the enable bit, and to clear the pending flags.
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ACE1501 Product Family Rev. 1.1
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