GTLP18T612 Datasheet, PDF (2/9 Pages) Fairchild Semiconductor – 18-Bit LVTTL/GTLP Universal Bus Transceiver

Pin Descriptions
Pin Names Description
OEAB
A-to-B Output Enable
(Active LOW) (LVTTL Level)
OEBA
B-to-A Output Enable
(Active LOW) (LVTTL Level)
CEAB
A-to-B Clock/LE Enable
(Active LOW) (LVTTL Level)
CEBA
B-to-A Clock/LE Enable
(Active LOW) (LVTTL Level)
LEAB
A-to-B Latch Enable
(Transparent HIGH) (LVTTL Level)
LEBA
B-to-A Latch Enable
(Transparent HIGH) (LVTTL Level)
V_REF
GTLP Input Threshold
Reference Voltage
CLKAB
A-to-B Clock (LVTTL Level)
CLKBA
B-to-A Clock (LVTTL Level)
A1–A18
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B1–B18
B-to-A Data Inputs or
A-to-B Open Drain Outputs
Connection Diagram
Functional Description
The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation
for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB
and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and
the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is
similar except that CEBA, OEBA, LEBA, and CLKBA are used.
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