GTLP16612 Datasheet, PDF (2/9 Pages) Fairchild Semiconductor – CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

Pin Descriptions
Pin
Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
CLKAB
CLKBA
V_REF
A1–A18
B1–B18
A-to-B Output Enable (Active LOW)
B-to-A Output Enable (Active LOW)
A-to-B Clock Enable (Active LOW)
B-to-A Clock Enable (Active LOW)
A-to-B Latch Enable (Transparent HIGH)
B-to-A Latch Enable (Transparent HIGH)
A-to-B Clock Pulse
B-to-A Clock Pulse
GTLP Input Reference Voltage
A-to-B TTL Data Inputs or
B-to-A 3-STATE Outputs
B-to-A GTLP Data Inputs or
A-to-B Open Drain Outputs
Connection Diagram
Functional Description
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins
operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches
and D-type flip-flops to allow data flow in transparent, latched and clock mode.
The functional operation is described in the truth table below.
Truth Table
(Note 1)
CEAB
X
L
L
X
X
L
L
H
Inputs
OEAB
LEAB
H
X
L
L
L
L
L
H
L
H
L
L
L
L
L
L
CLKAB
X
H
L
X
X
↑
↑
X
Output
B
A
X
Z
X B₀(Note 2)
X B₀(Note 3)
L
L
H
H
L
L
H
H
X B₀(Note 3)
Mode
Latched
storage
of A data
Transparent
Clocked storage
of A data
Clock inhibit
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low.
Note 3: Output level before the indicated steady-state input conditions were established.
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