GTLP16612 Datasheet, PDF(1/9 Page) Fairchild Semiconductor – CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

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GTLP16612 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

March 1995

Revised October 1998

GTLP16612

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description

The GTLP16612 is an 18-bit universal bus transceiver

which provides TTL to GTLP signal level translation. The

device is designed to provide a high speed interface

between cards operating at TTL logic levels and a back-

plane operating at GTLP logic levels. High speed back-

plane operation is a direct result of GTLPâs reduced output

swing (<1V), reduced input threshold levels and output

edge rate control which minimizes signal settling times.

GTLP is a Fairchild Semiconductor derivative of the Gun-

ning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Fairchildâs GTLP has internal edge-rate control and is Pro-

cess, Voltage, and Temperature (PVT) compensated. Its

function is similar to BTL or GTL but with different driver

output levels and receiver threshold. GTLP output low volt-

age is typically less than 0.5V, the output high is 1.5V and

the receiver threshold is 1.0V.

Features

s Bidirectional interface between GTLP and TTL logic

levels

s Designed with Edge Rate Control Circuit to reduce

output noise

s VREF pin provides external supply reference voltage for

receiver threshold

s Submicron Core CMOS technology for low power

dissipation

s Special PVT Compensation circuitry to provide consis-

tent performance over variations of process, supply

voltage and temperature

s 5V tolerant inputs and outputs on A-Port

s Bus-Hold data inputs on A-Port to eliminate the need for

external pull-up resistors for unused inputs

s Power up/down high impedance

s TTL compatible Driver and Control inputs

s A-Port outputs source/sink â32 mA/+32 mA

s Flow-through architecture optimizes PCB layout

s Open drain on GTLP to support wired-or connection

Ordering Code:

Order Number Package Number

Package Description

GTLP16612MEA

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300â Wide

GTLP16612MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter âXâ to the ordering code.

www.fairchildsemi.com

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