FDMS86102LZ Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – N-Channel Power Trench® MOSFET 100 V, 22 A, 25 mΩ

Electrical Characteristics T_J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV_DSS
ΔBV_DSS
ΔT_J
I_DSS
I_GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I_D = 250 μA, V_GS = 0 V
I_D = 250 μA, referenced to 25 °C
V_DS = 80 V, V_GS = 0 V
V_GS = ±20 V, V_DS = 0 V
100
V
70
mV/°C
1
μA
±10 μA
On Characteristics
V_GS(th)
ΔV_GS(th)
ΔT_J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
r_DS(on)
Static Drain to Source On Resistance
g_FS
Forward Transconductance
V_GS = V_DS, I_D = 250 μA
1.0
I_D = 250 μA, referenced to 25 °C
V_GS = 10 V, I_D = 7 A
V_GS = 4.5 V, I_D = 5.8 A
V_GS = 10 V, I_D = 7 A, T_J = 125 °C
V_DS = 5 V, I_D = 7 A
1.5
-6
18.6
23.5
31.2
26
2.5
V
mV/°C
25
37
mΩ
42
S
Dynamic Characteristics
C_iss
C_oss
C_rss
R_g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V_DS = 50 V, V_GS = 0 V,
f = 1 MHz
979 1305 pF
175 235 pF
8.9
15
pF
0.9
Ω
Switching Characteristics
t_d(on)
t_r
t_d(off)
t_f
Q_g(TOT)
Q_g(TOT)
Q_gs
Q_gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
V_DD = 50 V, I_D = 7 A,
V_GS = 10 V, R_GEN = 6 Ω
V_GS = 0 V to 10 V
V_GS = 0 V to 4.5 V
V_DD = 50 V,
I_D = 7 A
6.7
14
ns
2.6
10
ns
19
35
ns
2.5
10
ns
16
22
nC
7.8
11
nC
2.4
nC
2.6
nC
Drain-Source Diode Characteristics
V_SD
Source to Drain Diode Forward Voltage
V_GS = 0 V, I_S = 7 A
V_GS = 0 V, I_S = 2 A
(Note 2)
(Note 2)
0.81 1.3
V
0.72 1.2
t_rr
Reverse Recovery Time
Q_rr
Reverse Recovery Charge
I_F = 7 A, di/dt = 100 A/μs
35
57
ns
25
40
nC
NOTES:
1. R_θJA is determined with the device mounted on a 1 in² pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R_θJC is guaranteed by design while R_θCA is determined by
the user's board design.
a. 50 °C/W when mounted on a
1 in² pad of 2 oz copper
b. 125 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting T_J = 25 °C; N-ch: L = 1 mH, I_AS = 13 A, V_DD = 90 V, V_GS = 10 V.
4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2011 Fairchild Semiconductor Corporation
2
FDMS86102LZ Rev. C
www.fairchildsemi.com