FAN4810 Datasheet, PDF (2/14 Pages) Fairchild Semiconductor – Power Factor Correction Controller

FAN4810
Pin Configuration
FAN4810
(Pin Out)
IEAO 1
16 VEAO
IAC 2
ISENSE 3
VRMS 4
CLKSD 5
15 VFB
14 VREF
13 VCC
12 PFC OUT
NC 6
11 CLK OUT
RAMP 1 7
10 GND
NC 8
9 GND
TOP VIEW
PRODUCT SPECIFICATION
Pin Description
Pin Name
Function
1
IEAO Slew rate enhanced PFC transconductance error amplifier output
2
I _AC
PFC AC line reference input to Gain Modulator
3
I_SENSE Current sense input to the PFC Gain Modulator
4
V_RMS PFC Gain Modulator RMS line voltage compensation input
5 CLKSD Turn on/off PWM clock without disturbing PFC out
6
NC
7 RAMP 1 Oscillator timing node; timing set by R_TC_T
8
NC
9
GND Ground
10
GND Ground
11 CLK OUT Clock signal synchronized to PFC frequency
12 PFC OUT PFC driver output
13
V_CC
Positive supply
14
V_REF Buffered output for the internal 7.5V reference
15
V_FB
PFC transconductance voltage error amplifier input
16 VEAO PFC transconductance voltage error amplifier output
2
REV. 1.0.12 9/24/03