74VHC164_99 Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – 8-Bit Serial-In, Parallel-Out Shift Register

Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q₀ the log-
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Function Table
Operating
Inputs
Outputs
Mode
MR A B Q₀ Q₁–Q₇
Reset (Clear)
L XX L
L–L
Shift
H
LL
L
Q₀–Q₆
H
LH
L
Q₀–Q₆
H
HL
L
Q₀–Q₆
H
HH
H
Q₀–Q₆
H = HIGH Voltage Levels
L = LOW Voltage Levels
X = Immaterial
Q = Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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