74LCX574_08 Datasheet, PDF (2/14 Pages) Fairchild Semiconductor – 74LCX574

Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE 1
D0 2
D1 3
D2 4
D3 5
D4 ₆
D5 7
D6 8
D7 9
GND 10
20 V_CC
19 O0
18 O1
17 O₂
16 O3
15 ^O4
14 O5
13 O6
12 O7
11 CP
Pad Assignments for DQFN
OE VCC
1 20
D₀ 2
19 O₀
D1 3
18 O₁
D2 4
17 O₂
D3 5
16 O₃
D4 6
D5 7
D6 8
D7 9
15 O₄
14 O₅
13 O₆
12 O₇
10 11
GND CP
(Top View)
Pin Descriptions
Pin Names
D₀–D₇
CP
OE
O₀–O₇
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Logic Diagram
CP
D0
D1
D2
CD
Q
CD
Q
CD
Q
Logic Symbol
D0 D1 D2 D3 D4 D5 D6 D7
CP
OE
O0 O1 O2 O3 O4 O5 O6 O7
Truth Table
Inputs Internal Outputs
OE CP D Q
H H L NC
O_n
Function
Z
Hold
H H H NC
H
L
H
H
H
L
Z
Hold
Z
Load
Z
Load
L
L
H
L
Data Available
L
H
L
H Data Available
L H L NC
NC No Change in Data
L H H NC
NC No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Functional Description
The LCX574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
state. Operation of the OE input does not affect the load-
ing of the flip-flops.
D3
D4
D5
D6
D7
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
OE
O₀
O₁
O2
O3
O4
O5
O6
O7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
©2006 Fairchild Semiconductor Corporation
74LCX574 Rev. 1.6.0
2
www.fairchildsemi.com