74LCX32373 Datasheet, PDF (2/8 Pages) Fairchild Semiconductor – Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs Preliminary

Preliminary
Connection Diagram
(Top Thru View)
Pin Descriptions
Pin Names
OE_n
LE_n
I₀ - I₃₁
O₀ - O₃₁
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FBGA Pin Assignments
1
2
3
4
5
6
A
O₁
O₀ OE₁ LE₁
I₀
I₁
B
O₃
O₂ GND GND I₂
I₃
C
O₅
O₄
V_CC V_CC
I₄
I₅
D
O₇
O₆ GND GND I₆
I₇
E
O₉
O₈ GND GND I₈
I₉
F
O₁₁
O₁₀ V_CC V_CC
I₁₀
I₁₁
G
O₁₃ O₁₂ GND GND I₁₂
I₁₃
H
O₁₄ O₁₅ OE₂ LE₂
I₁₅
I₁₄
J
O₁₇ O₁₆ OE₃ LE₃
I₁₆
I₁₇
K
O₁₉ O₁₈ GND GND I₁₈
I₁₉
L
O₂₁
O₂₀ V_CC V_CC
I₂₀
I₂₁
M
O₂₃ O₂₂ GND GND I₂₂
I₂₃
N
O₂₅ O₂₄ GND GND I₂₄
I₂₅
P
O₂₇
O₂₆ V_CC V_CC
I₂₆
I₂₇
R
O₂₉ O₂₈ GND GND I₂₈
I₂₉
T
O₃₀ O₃₁ OE₄ LE₄
I₃₁
I₃₀
Truth Table
Functional Description
The LCX32373 contains thirty-two D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each
byte. When the Latch Enable (LE_n) input is HIGH, data on
the I_n enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
Inputs
Outputs
LE_n
OE_n
I_n
O_n
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O₀
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O₀ = Previous O₀ before HIGH-to-LOW transition of Latch Enable
its I input changes. When LE_n is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition of LE_n. The
3-STATE standard outputs are controlled by the Output
Enable (OE_n) input. When OE_n is LOW, the standard out-
puts are in the 2-state mode. When OE_n is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
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