74F899 Datasheet, PDF (2/12 Pages) Fairchild Semiconductor – 9-Bit Latchable Transceiver with Parity Generator/Checker

Input Loading/Fan-Out
Pin Names
Description
A₀–A₇
B₀–B₇
APAR
BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Data Inputs/
Data Outputs
Data Inputs/
Data Outputs
A Bus Parity
Input/Output
B Bus Parity
Input/Output
Parity Select Input
Output Enable Inputs
Mode Select Input
Latch Enable Inputs
Error Signal Outputs
HIGH/LOW
U.L.
Input I_IH/I_IL
HIGH/LOW
Output I_OH/I_OL
1.0/1.0
20 µA/−0.6 mA
150/40
−3 mA/24 mA
1.0/1.0
20 µA/−0.6 mA
600/106.6
−12 mA/64 mA
1.0/1.0
20 µA/−0.6 mA
150/40
−3 mA/24 mA
1.0/1.0
20 µA/−0.6 mA
600/106.6
−12 mA/64 mA
1.0/1.0
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
50/33.3
−1 mA/20 mA
Pin Descriptions
Pin Names
A₀–A₇
B₀–B₇
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Description
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for EVEN Parity
Output Enables for A or B Bus, Active LOW
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH for Transparent Mode
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
• Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
• Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
• Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
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