74F657 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal transceiver with 8-bit parit generator/checker

Unit Loading/Fan Out
Pin Names
Description
A₀–A₇
B₀–B₇
T/R
OE
PARITY
ODD/EVEN
ERROR
Data Inputs/
3-STATE Outputs
Data Inputs/
3-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/
3-STATE Output
ODD/EVEN Parity Input
Error Output
Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A Port to the
B Port; Receive (active LOW) enables data from the B Port
to the A Port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B Ports by placing
them in a HIGH-Z condition when the Output Enable input
is HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A Port are
HIGH and compares these with the condition of the parity
U.L.
HIGH/LOW
4.5/0.15
150/40 (33.3)
3.5/0.117
600/106.6 (80)
2.0/0.067
2.0/0.067
3.5/0.117
600/106.6 (80)
1.0/0.033
600/106.6 (80)
Input I_IH/I_IL
Output I_OH/I_OL
90 µA/− 90 µA
−3 mA/24 mA (20 mA)
70 µA/−70 µA
−12 mA/64 mA (48 mA)
40 µA/−40 µA
40 µA/−40 µA
70 µA/−70µA
−12 mA/64 mA (48 mA)
20 µA/−20 µA
−12 mA/64 mA (48 mA)
select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
Function Table
Function Table
Input/
Number of
Inputs
Output
Outputs
Inputs that
are HIGH
ODD/
Outputs
OE T/R
Parity ERROR
EVEN
Mode
0, 2, 4, 6, 8 L H H
H
Z Transmit
LH L
L
Z Transmit
LL H
H
H Receive
LL H
L
L Receive
LL L
H
L Receive
LL L
L
H Receive
1, 3, 5, 7
LH H
L
Z Transmit
LH L
H
Z Transmit
LL H
H
L Receive
LL H
L
H Receive
LL L
H
H Receive
LL L
L
L Receive
Immaterial H X X
Z
Z
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Inputs
OE
T/R
L
L
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Outputs
Bus B Data to Bus A
Bus A Data to Bus B
High-Z State
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