74F552 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Octal registered transceiver with parity and flags 3-State

Logic Symbols
IEEE/IEC
Unit Loading/Fan Out
Pin Names
A₀–A₇
B₀–B₇
FR
FS
PARITY
ERROR
CER
CES
CPR
CPS
OEBR
OEAS
Description
A-to-B Port Data Inputs or
U.L.
HIGH/LOW
3.5/1.083
Input I_IH/I_IL
Output I_OH/I_OL
70 µA/−0.65 mA
B-to-A 3-STATE
150/40 (33.3) −3 mA/24 mA (20 mA)
B-to-A Transceiver Inputs or
3.5/1.083
70 µA/−0.65 mA
A-to-B 3-STATE Output
B Port Flag Output
600/106.6 (80) −12 mA/64 mA (48 mA)
50/33.3
−1 mA/20 mA
A Port Flag Output
50/33.3
−1 mA/20 mA
Parity Bit Transceiver Input or Output
3.5/1.083
70 µA/−0.65 mA
600/106.6 (50) −12 mA/64 mA (48 mA)
Parity Check Output (Active LOW)
50/33.3
−1 mA/20 mA
R Registers Clock Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
S Registers Clock Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
R Registers Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
S Registers Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
B Port and PARITY Output Enable (Active LOW)
1.0/2.0
20 µA/−1.2 mA
and Clear FR Input (Active Rising Edge)
A Port Output Enable (Active LOW)
1.0/2.0
20 µA/−1.2 mA
and Clear FS Input (Active Rising Edge)
www.fairchildsemi.com
2