74F543_00 Datasheet, PDF (2/7 Pages) Fairchild Semiconductor – Octal Registered Transceiver

Unit Loading/Fan Out
Pin Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A₀–A₇
B₀–B₇
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40 (33.8)
3.5/1.083
600/106.6 (80)
Input I_IH/I_IL
Output I_OH/I_OL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
70 µA/−650 µA
−3 mA/24 mA (20 mA)
70 µA/−650 µA
−12 mA/64 mA (48 mA)
Functional Description
The F543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A₀–A₇ or
take data from B₀–B₇, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
Logic Diagram
Data I/O Control Table
Inputs
Latch
Output
CEAB LEAB OEAB
Status
Buffers
H
X
X
Latched
High Z
X
H
X
Latched
—
L
L
X
Transparent
—
X
X
H
—
High Z
L
X
L
—
Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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