74F543_00 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Octal Registered Transceiver

April 1988
Revised October 2000
74F543
Octal Registered Transceiver
General Description
The F543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA.
Features
s 8-bit octal transceiver
s Back-to-back registers for storage
s Separate controls for data flow in each direction
s A outputs sink 24 mA
s B outputs sink 64 mA
Ordering Code:
Order Number Package Number
Package Description
74F543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F543MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F543PC
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
74F543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS009554
www.fairchildsemi.com