74F524 Datasheet, PDF (2/9 Pages) NXP Semiconductors – 8-bit register comparator open-collector 3-State

Unit Loading/Fan Out
Pin Names
Description
U.L.
HIGH/LOW
Input I_IH/I_IL
Output I_OH/I_OL
S₀, S₁
C/SI
Mode Select Inputs
Status Priority or Serial Data Input
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
SE
Status Enable Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
M
Compare Mode Select Input
1.0/1.0
20 µA/−0.6 mA
I/O₀–I/O₇ Parallel Data Inputs or
3-STATE Parallel Data Outputs
3.5/1.083
150/40 (33.3)
70 µA/−0.65 mA
−3 mA/24 mA (20 mA)
C/SO
Status Priority or Serial Data Output
50/33.3
−1 mA/20 mA
LT
Register Less Than Bus Output
OC (Note 1) /33.3 (Note 1) /20 mA
EQ
Register Equal Bus Output
OC(Note 1) /33.3 (Note 1) /20 mA
GT
Note 1: OC = Open Collector
Register Greater Than Bus Output
OC(Note 1) /33.3 (Note 1) /20 mA
Number Representation Select Table
M
Operation
L
Magnitude Compare
H
Twos Complement Compare
Select Truth Table
S₀
S₁
Operation
L
L Hold—Retains Data in Shift Register
L
H Read—Read Contents in Register onto Data Bus,
Data Remains in Register Unaffected by Clock
H
L Shift—Allows Serial Shifting on Next Rising Clock Edge
H
H Load—Load Data on Bus into Register
Status Truth Table
(Hold Mode)
SE
C/SI
H
H
L
L
X
L
H
L
H
H
H
H
L
H
1 = HIGH if data are equal, otherwise LOW
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Inputs
Data Comparison
X
O_A–O_H > I/O₀–I/O₇
O_A–O_H = I/O₀–I/O₇
O_A–O_H < I/O₀–I/O₇
O_A–O_H > I/O₀–I/O₇
O_A–O_H = I/O₀–I/O₇
O_A–O_H < I/O₀–I/O₇
Outputs
EQ
GT
LT
H
H
H
L
H
H
H
H
H
L
H
H
L
H
L
H
L
L
L
L
H
C/SO
1
L
L
L
L
H
L
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