74F524 Datasheet, PDF (1/9 Pages) NXP Semiconductors – 8-bit register comparator open-collector 3-State

April 1988
Revised August 1999
74F524
8-Bit Registered Comparator
General Description
The 74F524 is an 8-bit bidirectional register with parallel
input and output plus serial input and output progressing
from LSB to MSB. All data inputs, serial and parallel, are
loaded by the rising edge of the input clock. The device
functions are controlled by two control lines (S₀, S₁) to exe-
cute shift, load, hold and read out.
An 8-bit comparator examines the data stored in the regis-
ters and on the data bus. Three true-HIGH, open-collector
outputs representing “register equal to bus”, “register
greater than bus” and “register less than bus” are provided.
These outputs can be disabled to the OFF state by the use
of Status Enable (SE). A mode control has also been pro-
vided to allow twos complement as well as magnitude com-
pare. Linking inputs are provided for expansion to longer
words.
Features
s 8-Bit bidirectional register with bus-oriented input-output
s Independent serial input-output to register
s Register bus comparator with “equal to”, “greater than”
and “less than” outputs
s Cascadable in groups of eight bits
s Open-collector comparator outputs for AND-wired
expansion
s Twos complement or magnitude compare
Ordering Code:
Order Number Package Number
Package Description
74F524SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F524PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009546
www.fairchildsemi.com