FAN7318B Datasheet, PDF (18/24 Pages) Fairchild Semiconductor – LCD Backlight Inverter Drive IC

Lamp Current Feedback Circuit
FAN7318B has four OLP pins for lamp current feedback
and protections. The inputs of four OLP pins are
connected to the internal half-wave and full-wave
rectifier circuits. The half-wave rectified signals of four
OLP inputs are connected to the maximum detector
circuit. The full-wave rectified signals of four OLP inputs
are connected to the minimum detector circuit.
Two inputs of the four OLP pins should be inverse
phase with the other two inputs.
Lamp Voltage Feedback Circuit
FAN7318B has four OLR pins for lamp voltage feedback
and protections. The inputs of four OLR pins are
connected to the internal full-wave rectifier circuit. The
full-wave rectified signals of the four OLR inputs are
connected to the maximum detector circuit.
Furthermore, they are connected to the minimum
detector circuit for protections.
Protections
The FAN7318B provides the following latch-mode
protections: Open-Lamp Regulation (OLR), Open-Lamp
Protection (OLP), Short-Lamp Protection (SLP), CMP-
High Protection and Thermal Shutdown (TSD). The latch
is reset when VIN falls to the UVLO voltage or ENA is
pulled down to GND.
The protection delay time can be adjusted by a capacitor
between the TIMER pin and GND.
Open-Lamp Regulation
When the maximum of the rectified OLR input voltages
(
Vmax
OLR
)
is
more
than
2V,
the
IC
enters
regulation
mode
and controls CMP voltage. The IC limits the lamp
voltage
by
decreasing
CMP
source
current.
If
V max
OLR
is
between 1.34V and 2V, CMP source current decreases
to 3.0µA. Then, if
V max
OLR
reaches 2V, CMP source current
decreases to 0µA, so the CMP voltage remains constant
and the lamp voltage also remains constant, as shown
in Figure 49.
Figure 49. Open-Lamp Regulation in Striking Mode
Finally, if
V max
OLR
is more than 2.2V, the error amplifier for
OLR is operating and CMP sink current increases, so
CMP voltage decreases and the lamp voltage maintains
the determined value, as shown in Figure 50.
Figure 48. Protection Timing Delay
Assume that the TIMER pin capacitor is 1µF.
The striking time is calculated as:
t_strike
= ^CΔVstr
I_{sur 1}
= ^{1μF • 3V}
2μ A
= 1.5s
(6)
The OVP and SLP delay time are calculated as:
t_{OVP _ SLP}
= ^CΔVnor
I_{sur 2}
= ^{1μF •1V}
50μ A
= 20ms
(7)
The CMP high protection and OLP delay time are
calculated as:
t_{OLP _ CMPH}
= ^CΔVnor
I_{sur 1}
= ^{1μF •1V}
2μ A
= 500ms
(8)
CMP
0
2.2V
2V
OLR 0
-2V
-2.2V
iCMP 0
2V OLR
2.2V OLR
Figure 50. 2.2V Open-Lamp Regulation
Over-Voltage Protection
In
normal
mode,
while
V max
OLR
is
higher
than
1.34V,
the
TIMER pin capacitor is charged by an internal current
source of 50µA. Once the TIMER reaches 1V, the IC
enters shutdown, as shown in Figure 51. This protection
is disabled in striking mode to ignite lamps reliably.
© 2009 Fairchild Semiconductor Corporation
FAN7318B • 1.0.0
18
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