FAN501A Datasheet, PDF (14/16 Pages) Fairchild Semiconductor – Offline DCM / CCM Flyback PWM Controller for Charger Applications

VDD Over-Voltage-Protection
VDD over-voltage protection prevents damage from over-
voltage exceeding the IC voltage rating. When VDD
exceeds 28 V due to an abnormal condition, protection
is triggered. This protection is typically caused by an
open circuit in the secondary-side feedback network.
Brownout Protection
Brownout protection is implemented through line voltage
detection circuit using the auxiliary winding, as shown in
Figure 25 and Figure 26. When the current flowing out
of the VS pin during the MOSFET conduction time is
smaller than 160 μA for longer than 30 ms, the brownout
protection is triggered.
Over-Temperature Protection (OTP)
If the junction temperature exceeds 140°C (TOTP), the
internal temperature-sensing circuit shuts down PWM
output and enters Latch Mode protection.
Fold-Back Point and Over-Voltage Protection (VS
OVP)
Generally, the fold-back point in CC regulation as output
drops is determined by the VDD-OFF level. Thus, the fold-
back level mainly depends on the characteristics of the
VDD diode and transformer. For VS pin voltage divider
design, RVS1 is obtained from Equation (8), and RVS2 is
determined by the VSOVP function as:
𝑅_{𝑉𝑆2} = 𝑅_{𝑉𝑆1} ∙
𝑉_{𝑂−𝑂𝑉𝑃}
𝑉_{𝑉𝑆−𝑂𝑉𝑃}
∙
𝑁_𝐴
𝑁_𝑆
−
1
−1
(11)
where VO-OVP is the output over-voltage protection
threshold level.
VS over-voltage protection prevents damage caused by
output over-voltage condition. Figure 34 shows the
internal circuit of VS OVP. When abnormal system
conditions occur that cause VS sampling voltage to
exceed VVS-OVP (3.2 V) for more than debounce
switching cycles (NVS-OVP), PWM pulses are disabled
and the FAN501A enters Latch Mode protection. VS
over-voltage conditions are usually caused by an open
circuit in the secondary-side feedback network or a fault
condition in the VS pin voltage divider resistors.
Aux.
RVS1
NA
RVS2
3.20V
S/H
DQ
Latch
Protection
PWM
VSOVP Dedounce
time
Counter
Figure 34. VS OVP Protection Circuit
Externally Triggered Shutdown
By pulling the SD pin voltage below threshold voltage,
VSD-TH (1.0 V); shutdown can be externally triggered and
the FAN501A enters Latch Mode protection. It can be
also used for external OTP protection by connecting an
NTC thermistor between the shutdown (SD)
programming pin and ground. An internal constant
current source, ISD (100 µA), introduces voltage drop
across the thermistor. Resistance of the NTC thermistor
becomes smaller as the ambient temperature increases,
which reduces the voltage drops across the thermistor.
When the voltage of the SD pin is less than threshold
voltage VSD-TH (1.0 V), OTP protection is triggered.
5V
100μA
NTC
Thermistor
1.0V
Latch
Protection
Figure 35. Thermal Shutdown Using SD Pin
© 2014 Fairchild Semiconductor Corporation
FAN501A • Rev. 1.0.0
14
www.fairchildsemi.com