FAN501A Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – Offline DCM / CCM Flyback PWM Controller for Charger Applications

The turn-off delay should be obtained by measuring the
time between the falling edge and actual turn-off instant
of MOSFET, as illustrated in Figure 27.
t_{OFF .DLY}
I_DS R_CS
R_CS I_DS
I _DS.SH R_CS ^I DS ^{PK R}CS
VO
VFB-Burst-H
VFB-Burst-L
VFB
I _D ^PK
N_P
N_S
I _DS.SH
N_P
N_S
Actual diode current
Estimated diode current
GATE
Figure 29. Burst-Mode Operation
GATE (# 2)
t_DIS
V_GS
Figure 27. CC Control Correction Concept
COMP
RCOMP
Aux.
NA
RVS1
RVS2 VS
CC Control
Correction
Line Signal
Line Voltage
Detector
Zero Current
Detector
VBLK
5V
ILVF
Pri.
NP
RLVF
IO Estimator
GATE
RCSF
CS
RCS
Figure 28. CC Correction Circuit
Pulse-by-Pulse Current Limit
Since the peak transformer current is controlled by a
feedback loop, the peak transformer current is not
properly controlled when the feedback loop is saturated
to HIGH, which typically occurs under startup or
overload conditions. To limit the current, a pulse-by-
pulse current limit forces the gate drive signal to turn off
when the CS pin voltage reaches the current-limit
threshold (VCS-LIM) in normal operation.
Burst Mode Operation
The power supply enters Burst Mode at no-load or
extremely light-load condition. As shown in Figure 29,
when VFB drops below VFB-Burst-L, the PWM output shuts
off and the output voltage drops at a rate dependent on
load current. This causes the feedback voltage to rise.
Once VFB exceeds VFB-Burst-H, the internal circuit starts to
provide a switching pulse. The feedback voltage then
falls and the process repeats. In this manner, Burst
Mode alternately enables and disables switching of the
MOSFET to reduce the switching losses in Standby
Mode. In Burst Mode, the operating current is reduced
from 3.5 mA to 250 μA to minimize power consumption.
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth of the EMI test equipment, allowing
compliance with EMI limitations.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for current-mode control and pulse-by-pulse
current limiting. A synchronized ramp signal with a
positive slope is added to the current-sense information
at each switching cycle, improving noise immunity
during current mode control and avoiding sub-harmonic
oscillation during CCM operation.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse by the spike, a 150 ns
leading-edge blanking time is incorporated.
Conventional RC filtering can therefore be omitted.
During this blanking period, the current-limit comparator
is disabled and it cannot switch off the gate driver.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter. Though slope
compensation helps alleviate this problem, precautions
should be taken to improve the noise immunity. Good
placement and layout practices are important. Avoid
long PCB traces and component leads and locate
bypass capacitor as close to the PWM IC as possible.
High Voltage (HV) Startup
Figure 30 shows the high-voltage (HV) startup circuit for
FAN501A applications. The JFET is used to internally
implement the high-voltage current source (see Figure
31 for characteristics). Technically, the HV pin can be
directly connected to voltage (VBLK) on an input bulk
capacitor. To improve reliability and surge immunity,
however, it is typical to use a ~100 kΩ resistor between
the HV pin and bulk capacitor voltage. The actual HV
current with a given bulk capacitor voltage and startup
resistor is determined by the intersection of V-I
characteristics line and load line, as shown in Figure 31.
© 2014 Fairchild Semiconductor Corporation
FAN501A • Rev. 1.0.0
12
www.fairchildsemi.com