FAN302UL Datasheet, PDF (14/19 Pages) Fairchild Semiconductor – PWM Controller for Low Standby Power Battery-Charger Applications

Figure 37. Auto-Restart Mode Operation
V_DL
N_P
Minimum
On Time
Modulation
Brownout
Protection
PWM
Control
Block
Current
Monitoring
Block
VS
RVS2
RVS1
CVS
N_A
Figure 39.VS Pin Current Sensing
FAN302UL modulates the minimum ON time of the
MOSFET such that it reduces as input voltage
increases, as shown Figure 40. This allows smaller
minimum ON time for high-line condition, ensuring Burst
Mode operation occurs at almost the same power level,
regardless of line voltage variation. The minimum ON
time is also related to the bundle frequency of Burst
Mode operation.
The VS current is also used for brownout protection.
When the current out of the VS pin while the MOSFET
is on is smaller than 47μA for longer than 10ms, the
brownout protection is triggered.
Figure 38. Latch-Mode Operation
V_DD Over-Voltage Protection
V_DD over-voltage protection prevents IC damage from
over-voltage exceeding the IC voltage rating. When the
V_DD voltage exceeds 26.5V due to abnormal conditions,
the protection is triggered. This protection is typically
caused by an open circuit of the secondary-side
feedback network.
Input Voltage Sensing and Brownout Protection
The FAN302UL indirectly senses input voltage using the
VS pin current while the MOSFET is turned on. Since
the VS pin voltage is clamped at 0.7V when the
MOSFET is turned on, the current flowing out of the VS
pin is approximately proportional to the input voltage, as
shown in Figure 38. Current flowing out of the VS pin is
calculated by:
I_{VS .ON}
=
(
N
N
A
P
V_DL
+ 0.7)
1
R_VS1
+
0.7
R_{VS 2}
≅
N_A
N_P
V_DL
R_VS1
(3)
Figure 40. Minimum On Time vs. VS Pin Current
Over-Temperature Protection (OTP)
The temperature-sensing circuit shuts down PWM
output if the junction temperature exceeds 140°C (t_OTP).
V_S Over-Voltage Protection (OVP)
V_S over-voltage protection prevents damage due to
output over-voltage conditions. Figure 41 shows the V_S
OVP protection method. When abnormal system
conditions occur that cause V_S to exceed 2.8V, after a
period of debounce time; PWM pulses are disabled and
FAN302UL enters Latch Mode until VDD drops to under
VDD-LH. By that time, PWM pulses revive. V_S over-voltage
conditions are usually caused by an open circuit of the
secondary-side feedback network or abnormal behavior
by the VS pin divider resistor.
© 2011 Fairchild Semiconductor Corporation
FAN302UL • Rev. 1.0.3
14
www.fairchildsemi.com