FAN6300A Datasheet, PDF (12/15 Pages) Fairchild Semiconductor – Highly Integrated Quasi-Resonant Current Mode PWM Controller

Current Sensing and PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
CS pin. The PWM duty cycle is determined by this
current-sense signal and VFB. When the voltage on CS
reaches around VLIMIT = (VFB-1.2)/3, the switch cycle is
terminated immediately. VLIMIT is internally clamped to a
variable voltage around 0.85V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking
time is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8V. During startup, the startup
capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until energy can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 10V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply VDD during startup.
V_DD Over-Voltage Protection
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
VDD over-voltage protection voltage (VDD-OVP) and lasts
for tVDDOVP, the PWM pulse is disabled until the VDD
voltage drops below the UVLO, then starts again.
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4μs (1.5μs for H version) blanking time
ignores the leakage inductance ringing. A voltage
comparator and a 2.5V reference voltage develop an
output OVP protection. The ratio of the divider
determines the sampling voltage of the stop gate, as an
optical coupler and secondary shunt regulator are used.
If the DET pin OVP is triggered, the power system enters
latch-mode until AC power is removed.
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Over-Power Compensation
To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of RDET is higher. RDET
also affects the H/L line constant power limit.
Figure 23. Voltage Sampled After 4μs
(1.5μs for FAN6300H version) Blanking Time
After Switch-Off Sequence
Short-Circuit and Open-Loop Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned-off, the supply voltage VDD begins decreasing.
When VDD goes below the PWM-off threshold of 10V,
VDD decreases to 8V, then the controller is totally shut
down. VDD is charged up to the turn-on threshold voltage
of 16V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
12
www.fairchildsemi.com