FAN6300A Datasheet, PDF (11/15 Pages) Fairchild Semiconductor – Highly Integrated Quasi-Resonant Current Mode PWM Controller

Operation Description
The FAN6300A/H PWM controller integrates designs to
enhance the performance of flyback converters. An
internal valley voltage detector ensures power system
operates at Quasi-Resonant (QR) operation across a
wide range of line voltage. The following descriptions
highlight some of the features of the FAN6300A/H.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, which are recommended as 1N4007 and 100kΩ.
Typical startup current drawn from the HV pin is 1.2mA
and it charges the hold-up capacitor through the diode
and resistor. When the VDD voltage level reaches VDD-ON,
the startup current switches off. At this moment, the VDD
capacitor only supplies the FAN6300A/H to maintain VDD
until the auxiliary winding of the main transformer
provides the operating current.
Valley Detection
The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors RDET and RA. RDET is recommended as
150kΩ to 220kΩ to achieve valley voltage switching.
When VAUX (in Figure 17) is negative, the DET pin
voltage is clamped to 0.3V.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference. In
Figure 19, once VFB is lower than VN, tOFF-MIN increases
linearly with lower VFB. The valley voltage detection
signal does not start until tOFF-MIN finishes. Therefore, the
valley detect circuit is activated until tOFF-MIN finishes,
which decreases the switching frequency and provides
extended valley voltage switching. However, in very light
load condition, it might fail to detect the valley voltage
after the tOFF-MIN expires. Under this condition, an internal
tTIME-OUT signal initiates a new cycle start after a 9μs
delay (with 5µs delay for H version). Figure 20 and
Figure 21 show the two different conditions.
t_{O FF -M IN}
2 .1 m s
38/13 μ s
8 /3μ s
1 .2 V
2 .1 V
VFB
Figure 19. VFB vs. tOFF-MIN Curve
Figure 17. Valley Detect Section
The internal timer (minimum tOFF time) prevents gate
retriggering within 8µs (3µs for H version) after the gate
signal going-low transition. The minimum tOFF limit
prevents system frequency being too high. Figure 18
shows a typical drain voltage waveform with first valley
switching.
Figure 20. QR Operation in Extended Valley Voltage
Detection Mode
Figure 18. First Valley Switching
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
Figure 21. Internal tTIME-OUT Initiates New Cycle After
Failure to Detect Valley Voltage
(with 5µs Delay for FAN6300H version)
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