FAN5354 Datasheet, PDF (12/14 Pages) Fairchild Semiconductor – 3MHz, 3A Synchronous Buck Regulator

If COUT is greater than 100μF, the regulator may fail to start
under load.
If an inductor value greater than 1.0μH is used, at least 30μF
of COUT should be used to ensure stability.
As can be seen in Figure 11 the lowest ∆VOUT is obtained
when the IC is in PWM mode and, therefore, operating at
3Mhz. In PFM mode, fSW is reduced, causing ∆VOUT to
increase. At extremely light loads, the output ripple
decreases, as the minimum frequency circuit becomes active
and the effective tON (high-side on-time) decreases.
ESL Effects
The ESL (Equivalent Series Inductance) of the output
capacitor network should be kept low to minimize the square
wave component of output ripple that results from the division
ratio COUT ESL and the output inductor (LOUT). The square
wave component due to the ESL can be estimated as:
ΔV_OUT(SQ)
≈
V_IN
• ^ESLCOUT
L1
(9)
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT=20μF, a single 22μF 0805 would
produce twice the square wave ripple of 2 x 10μF 0805.
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805s have lower ESL than 1206s. If low
output ripple is a chief concern, some vendors produce 0508
or 0612 capacitors with ultra-low ESL. Placing additional
small value capacitors near the load also reduces the high-
frequency ripple components.
Input Capacitor
The 10μF ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
reduce under-damped ringing that can occur between the
inductance of the power source leads and CIN.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
Layout Recommendations
The layout recommendations below highlight various top-
copper planes by using different colors. It includes COUT3 to
demonstrate how to add COUT capacitance to reduce ripple
and transient excursions. The inductor in this example is the
TDK VLC5020T-R47N.
VCC and VIN should be connected together by a thin trace
some distance from the IC, or through a resistor (shown as
R3 below), to isolate the switching spikes on PVIN from the
IC’s bias supply on VCC. If PCB area is at a premium, the
connection between PVIN and VCC can be made on another
PCB layer through vias. The via impedance provides some
filtering for the high-frequency spikes generated on PVIN.
PGND and AGND connect through the thermal pad of the IC.
Extending the PGND and AGND planes improves IC cooling.
The IC analog ground (AGND) is bonded to P1 between pins
1 and 12. Large AC ground currents should return to pins 3
and 4 (PGND) either through the copper under P1 between
pins 6 and 7 or through a direct trace from pins 3 and 4 (as
shown for COUT1-COUT3).
EN and PGOOD connect through vias to the system control
logic.
CIN1 is an optional device used to provide a lower
impedance path for high-frequency switching edges/spikes,
which helps to reduce SW node and VIN ringing. CIN should
be placed as close as possible between PGND and VIN as
shown below.
PGND connection back to inner planes should be
accomplished as series of vias distributed among the COUT
return track and CIN return plane between pins 6 and 7.
COUT3
VOUT
COUT2
10μF
0805
10μF
0805
0402
AGND
COUT1
10μF
0805
L1
1
2
3
PGND
4
5
6
SW
12
FAN5354 ₁₁
CVCC
P1
(GND)
10
9 VCC
8
7
CIN1 0402
10μF
0805
CIN
0.47μH
5 x 5 mm
PGND
R3
VIN
© 2009 Fairchild Semiconductor Corporation
FAN5354 • Rev. 1.0.4
Figure 30. 3A Layout Recommendation
12
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