FAN5038 Datasheet, PDF (12/15 Pages) Fairchild Semiconductor – Dual Voltage Controller for DSP Power

FAN5038
PRODUCT SPECIFICATION
copper on the PCB inner layers, it is recommended to use
those layers to route the high current paths in the design.
Capacitor Placement
One of the keys to a successful switch-mode power supply
design is correct placement of the low ESR capacitors.
Decoupling capacitors serve two purposes; first there must
be enough bulk capacitance to support the expected transient
current, and second, there must be a variety of values and
capacitor types to provide noise supression over a wide
range of frequencies. The low ESR capacitors on the input
side (5V) of the FET must be located close to the drain of the
power FET. Minimizing parasitic inductance and resistance
is critical in supressing the ringing and noise spikes on the
power supply. The output low ESR capacitors need to be
placed close to the output sense resistor to provide good
decoupling at the voltage sense point. One of the characteris-
tics of good low ESR capacitors is that the impedance gradu-
ally increases as the frequency increases. Thus for high
frequency noise supression, good quality low inductance
ceramic capacitors need to be placed in parallel with the low
ESR bulk capacitors. These can usually be 0.1µF 1206 sur-
face mount capacitors.
Example of
a Good layout
SDRV
9
8
10
7
11
6
12
5
Noisy Signal is
routed away from
13
4
quiet pins and
14
3
trace length is
kept under 0.5 in. ^CEXT
15
2
16
1
Example of
a Problem layout
IFBL
IFBH
VREF
SWDRV
9
10
11
12
13
14
CEXT 15
16
8
7
6
5
4
IFBL
3
IFBH
2
VREF
1
= “Quiet” Pins
Noisy Signal
radiates onto
quiet pins
and trace is
too long.
Figure 3. Examples of good and poor layouts
Power and Ground Connections
The connection of VCCA to the 5V power supply plane
should be short and bypassed with a 0.1µF directly at the
VCCA pin of the FAN5038. The ideal connection would be a
via down to the 5V power plane. A similar arrangement
should be made for the VCCL pin that connects to +12V,
though this one is somewhat less critical since it powers only
the linear op-amp. Each ground should have a separate via
connection to the ground plane below.
MOSFET Gate Bias
+12V
+5V
47 W
VCCP
Q1
SDRV
1uF
L1
VO
RSENSE
D1
CBULK
GNDP
Figure 4. 12V Gate Bias Configuration
12
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