FAN5038 Datasheet, PDF (10/15 Pages) Fairchild Semiconductor – Dual Voltage Controller for DSP Power

FAN5038
PRODUCT SPECIFICATION
Output Voltage Selection
The FAN5038 precision reference is trimmed to be 1.5V
nominally. When using the FAN5038, the system designer
has complete flexibility in choosing the output voltage for
each regulator from 1.5V to 3.6V. This is done by appropri-
ately selecting the feedback resistors. These could be 0.1%
resistors to realize optimum output accuracy. The following
equations determine the output voltages of the two regulators:
Switching Regulator:
V_OUT
=
1.5
×


-R----8--R--+---8--R-----3-_
Linear Regulator:
V_OUT = 1.5 × _^{R-----1--R-0----1+---0--R-----9-}_
where R8 > 1.5kΩ and (R8 + R3) ≤ 25kΩ and R10 > 1.5kΩ
and (R9 + R10) ≤ 25kΩ
Example:
For 3.3V,
V_OUT
=
1.5
×


R-----1--R-0----1+---0--R-----9-_
=
1.5
×


1----2---k-1---+0----k-1---0----k-_
=
3.3V
Input Capacitors
The number of input capacitors required for the FAN5038 is
dependent on their ripple current rating, which assures their
rated life. The number required may be determined by
No. Caps = ^I---o--^u---^t--^*----D-----C------–----D-----C----²-
(2)
I_rating
where the duty cycle DC = Vout/Vin. For example, with a
1.5V output at 4A, 5V input, and using the Sanyo capacitors
specified in Table 1 which have a 1.9A ripple current rating,
we have DC = 1.5/5 = 0.3, and
No. Caps = -4---^∗-------0---.--3----–-----0---.-3---²- = 0.96
1.9
so that we need 1 input capacitor.
Linear Regulator Design Considerations
Figure 1 shows the application schematic for the FAN5038
with an NPN used for the linear regulator.
Careful consideration must be given to the base current of
the power NPN device. The base current to the power NPN
device is limited by:
• The FAN5038 op-amp output current (50mA)
• The internal power dissipation of the FAN5038 package
• The β of the power NPN device.
The internal FAN5038 power dissipation is the most impor-
tant limitation for this application. For optimum reliability,
we require that the junction temperature not exceed 130°C;
thus we can calculate the maximum power dissipation allow-
able for this 16-lead SOIC package as follows:
P_D
=
T----_{J---(-m----a---x---)---–----T----A--}
R_ΘJA
If we assume that the ambient temperature T_A is 70°C and
the thermal resistance of the 16-lead SOIC package is
112°C/W, then the maximum power dissipation for the IC is:
P_D
=
-1---3---0----–-----7---0-
112
≤
0.533W
P_D = P_SW + P_LR =
(35mA × 5.25V) + (12.6V – V_OUT – V_BE) × I_OL ≤ 0.533W
where PSW is the internal power dissipation of the switching
regulator and PLN is the internal power dissipation of the linear
regulator. IOL is the linear regulator op-amp output current.
For VOUT = 3.3V nominal, the worst case output will be
determined by the current used.
For example, for a worst case VOUT = 3.135V, the maximum
op-amp output current is:
I_OL = ^0---₍-.-51---32---3.--6-W--V------––----⁽-3-3--.-15---3-m--5---A-V-----^×_{–----5-0--.-.-28---5-V--V--)}---⁾- ≤ 40mA
β
≥
5----0---0---m-----A---
40mA
=
12.5
The power NPN transistor must have a minimum β of 12.5 at
I_L = 500mA in order to meet the internal power dissipation
limit of the 16-SOIC package.
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REV. 1.0.2 7/6/00