FAN302HLMY Datasheet, PDF (12/18 Pages) Fairchild Semiconductor – PWM Controller for Low Standby Power Battery- Charger Applications — mWSaver™ Technology

CCM Prevention Function
Even if the power supply is designed to operate in DCM,
it can go into CCM when there is not enough design
margin to cover all the circuit parameter variations and
operating conditions. FAN302HLMY_F117 has a CCM-
prevention function that delays the next cycle turn-on of
MOSFET until ZCD on the VS pin is obtained, as shown
in Figure 31. To guarantee stable DCM operation,
FAN302HLMY_F117 prohibits the turn-on of the next
switching cycle for 10% of its switching period after ZCD
is obtained. In Figure 31, the first switching cycle has
ZCD before 90% of its original switching period and,
therefore, the turn-on instant of the next cycle is
determined without being affected by the ZCD instant.
The second switching cycle does not have ZCD by the
end of the original switching period; thus, the turn-on of
the third switching cycle occurs after ZCD is obtained,
with a delay of 10% of its original switching period. The
minimum switching frequency that CCM prevention
function allows is 18kHz (f_OSC-CM-MIN). If the ZCD is not
given until the end of maximum switching period of
55.6µs (1/18kHz), the converter can go into CCM
operation, losing output regulation.
Figure 32. Power Limit Mode Operation
High-Voltage Startup
Figure 33 shows the high-voltage (HV) startup circuit.
Internally, JFET is used to implement the high-voltage
current source, whose characteristics are shown in
Figure 34. Technically, the HV pin can be directly
connected to the DC link (V_DL). To improve reliability
and surge immunity; it is typical to use about a 100kΩ
resistor between the HV pin and the DC link. The actual
HV current with given DC link voltage and startup
resistor is determined by the intersection of V-I
characteristics line and load line, as shown in Figure 34.
During startup, the internal startup circuit is enabled and
the DC link supplies the current, I_HV, to charge the hold-
up capacitor, C_VDD, through R_START. When the V_DD
voltage reaches V_DD-ON, the internal HV startup circuit is
disabled and the IC starts PWM switching. Once the HV
startup circuit is disabled, the energy stored in C_VDD
should supply the IC operating current until the
transformer auxiliary winding voltage reaches the
nominal value. Therefore, C_VDD should be designed to
prevent V_DD from dropping to V_DD-OFF before the auxiliary
winding builds up enough voltage to supply V_DD.
Figure 31. CCM Prevention Function
Power Limit Mode
When the sampled voltage of VS (V_SH) drops below V_S-
CM-MIN ^{(0.55V), FAN302HLMY_F117 enters constant}
Power Limit Mode, where the primary-side current-limit
voltage (V_CS) changes from V_STH (0.8V) to V_STH-VA (0.3V)
to avoid V_S sampling and ZCD, as shown in Figure 32.
Once V_S sampling voltage is higher than V_S-CM-MAX
(0.75V), the V_CS returns to V_STH. This mode prevents the
power supply from going into CCM and losing output
regulation when the output voltage is too low. This
effectively protects the power supply when there is a
fault condition in the load, such as output short or
overload. This mode also implements soft-start by
limiting the transformer current until V_S sampling voltage
reaches V_S-CM-MAX (0.75V).
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.1
12
Figure 33. HV Startup Circuit
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