FAN2110 Datasheet, PDF (12/17 Pages) Fairchild Semiconductor – TinyBuck™, 3-24V Input, 10A, High-Efficiency, Integrated Synchronous Buck Regulator

Circuit Description
PWM Generation
Refer to Figure 2 for the PWM control mechanism.
FAN2110 uses the summing-mode method of control to
generate the PWM pulses. An amplified current-sense
signal is summed with an internally generated ramp and
the combined signal is compared with the output of the
error amplifier to generate the pulse width to drive the
high-side MOSFET. Sensed current from the previous
cycle is used to modulate the output of the summing
block. The output of the summing block is also
compared against a voltage threshold set by the RLIM
resistor to limit the inductor current on a cycle-by-cycle
basis. RRAMP resistor helps set the charging current for
the internal ramp and provides input voltage feed-
forward function. The controller facilitates external
compensation for enhanced flexibility.
Initialization
Once VCC exceeds the UVLO threshold and EN is
HIGH, the IC checks for a shorted FB pin before
releasing the internal soft-start ramp (SS).
If the parallel combination of R1 and RBIAS is ≤ 1KΩ, the
internal SS ramp is not released and the regulator does
not start.
EN
1.35V
2400 CLKs
0.8V
FB
1. 0V
0. 8V
F ault
La t c h
Enable
SS
3200 CLKs
T0.8
4000 CLKs
T1.0
Figure 31. Soft-Start Timing Diagram
VCC UVLO or toggling the EN pin discharges the
internal SS and resets the IC. In applications where
external EN signal is used, VIN and VCC should be
established before the EN signal comes up to prevent
skipping the soft-start function.
Enable
FAN2110 has an internal pull-up to the enable (EN) pin
so that the IC is enabled once VCC exceeds the UVLO
threshold. Connecting a small capacitor across EN and
AGND delays the rate of voltage rise on the EN pin. The
EN pin also serves for the restart whenever a fault
occurs (refer to the Auto-Restart section). If the
regulator is enabled externally, the external EN signal
should go HIGH only after VCC is established. For
applications where such sequencing is required,
FAN2110 can be enabled (after the VCC comes up) with
external control, as shown in Figure 30.
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of VREF (~0.76V). This enables the regulator to startup
on a pre-biased output and ensures that pre-biased
outputs are not discharged during the soft-start cycle.
Protections
The converter output is monitored and protected
against extreme overload, short-circuit, over-voltage,
under-voltage, and over-temperature conditions.
Under-Voltage Shutdown
If voltage on the FB pin remains below the under-
voltage threshold for 16 consecutive clock cycles, the
fault latch is set and the converter shuts down. This
protection is not active until the internal SS ramp
reaches 1.0V during soft-start.
Figure 30. Enabling with External Control
Soft-Start
Once internal SS ramp has charged to 0.8V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0V (T1.0), the fault latch is inhibited.
To avoid skipping the soft-start cycle, it is necessary to
apply VIN before VCC reaches its UVLO threshold. Normal
sequence for powering up would be VINÆVCCÆEN.
Soft-start time is a function of oscillator frequency.
Over-Voltage Protection
If voltage on the FB pin exceeds 115% of VREF for two
consecutive clock cycles, the fault latch is set and
shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The OV/UV fault protection circuits above are active all
the time, including during soft-start.
© 2008 Fairchild Semiconductor Corporation
FAN2110 • Rev. 1.0.2
12
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