FAN103_10 Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – Primary-Side-Regulation PWM Controller (PWM-PSR)

Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V and 5V, respectively. During startup, the hold-up
capacitor must be charged to 16V through the startup
resistor to enable the FAN103. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
is not allowed to drop below 5V during this startup
process. This UVLO hysteresis window ensures that
hold-up capacitor properly supplies VDD during startup.
Protections
The FAN103 has several self-protection functions, such
as Over-Voltage Protection (OVP), Over-Temperature
Protection (OTP), and Pulse-by-Pulse Current limit. All
the protections are implemented as auto-restart mode.
Once an abnormal condition occurs, switching is
terminated and the MOSFET remains off, causing VDD
to drop. When VDD drops to the VDD turn-off voltage of
5V, the internal startup circuit is enabled again, then the
supply current drawn from HV pin charges the hold-up
capacitor. When VDD reaches the turn-on voltage of
16V, FAN103 resumes normal operation. In this
manner, the auto-restart alternately enables and
disables the switching of the MOSFET until the
abnormal condition is eliminated (see Figure 26).
Figure 26. Auto Restart Operation
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
Pulse-by-pulse Current Limit
When the sensing voltage across the current sense
resistor exceeds the internal threshold of 0.8V, the
MOSFET is turned off for the remainder of switching
cycle. In normal operation, the pulse-by-pulse current
limit is not triggered since the peak current is limited by
the control loop.
Leading-Edge Blanking (LEB)
Each time the power MOSFET switches on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. Conventional RC filtering can
be omitted. During this blanking period, the current-
limit comparator is disabled and cannot switch off the
gate driver.
Gate Output
The FAN103 output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
15V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Built-in Slope Compensation
The sensed voltage across the current sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The FAN103 has a
synchronized, positive-slope ramp built-in at each
switching cycle.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode. While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FAN103, and increasing
the power MOS gate resistance is advised.
V_DD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage from over-
voltage conditions. If the VDD voltage exceeds 28V at
open-loop feedback condition, OVP is triggered and the
PWM switching is disabled. The OVP has a de-bounce
time (typically 200µs) to prevent false triggering due to
switching noises.
© 2010 Fairchild Semiconductor Corporation
FAN103 • Rev. 1.0.3
12
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