74LCX74_08 Datasheet, PDF (12/13 Pages) Fairchild Semiconductor – 74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs

Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
0.45
6.10
R0.09 min
12.00°_{TOP & BOTTOM}
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
1.00
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
R0.09min
Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.0
12
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