HCPL0601R2 Datasheet, PDF (11/18 Pages) Fairchild Semiconductor – High Speed-10 MBit/s Logic Gate Optocouplers

Pulse Gen.
tf = tr = 5 ns
ZO = 50 Ω
1
2
Input
Monitor
3
(IF)
47Ω ⁴
VCC 8
7
.1μf
Bypass
6
GND 5
+5V
Pulse Gen.
ZO = 50 Ω
tf = tr = 5 ns
IF
Input
RL
Monitoring
Node
Output
(VO)
CL
RM
Test Circuit for HCPL0600,
HCPL0601 and HCPL0611
Dual Channel
1
VCC 8
2
7
3
6
4
5
GND
+5 V
RL
0.1μF
Bypass
Output VO
Monitoring
Node
CL*
Input
(I _F)
t_PHL
Output
(V_O)
Output
(V_O)
t_f
Test Circuit for HCPL0637,
HCPL0638 and HCPL0639
I _F = 7.5 mA
I _F = 3.75 mA
t_PLH
90%
10 %
1.5 V
t_r
Fig. 20 Test Circuit and Waveforms for t_PLH, t_PHL, t_r and t_f.
Pulse
Generator
tr = 5ns
Z_O = 50Ω
1
7.5 mA
2
3
4
Input
Monitor
(V _E)
+5V
V_CC
8
7
.1μf
bypass
6
5
GND
R_L
Output
(V_O)
C_L
Input
(V_E )
t_EHL
Output
(V_O)
Fig. 21 Test Circuit t_EHL and t_ELH.
t _ELH
3.0 V
1.5 V
1.5 V
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.9
11
www.fairchildsemi.com