FMS6407_05 Datasheet, PDF (11/17 Pages) Fairchild Semiconductor – Triple Video Drivers with Selectable HD/Progressive/SD/Bypass Filters

FMS6407
DATA SHEET
and an external sync signal must be input on the SYNC_IN
pin. Refer to the External Sync section for more details. The
timing required for this operating mode is shown in Figure 2.
0dB Gain 6dB
950mV 1650mV
250mV 250mV
0mV 0mV
Av = 1 (0dB) or 2 (6dB)
Av*700mV
Active
Video
True Sync Position
T1
Allowable SYNC_IN
Required Blanking Offset
T2
Figure 2. Bi-Level External
Sync Clamping and Bias
HD Video Sync Processing
When the input signal is a high definition signal, the tri-level
sync pulse is too short to allow proper clamp operation.
Rather than clamp during the sync pulse, the sync pulse is
located and the signal is clamped to the blanking level. This
is done in such a way that the sync tip will still be set to
approximately 250mV. The EXT_SYNC control input
selects the sync stripper output or the SYNC_IN pin for use
by the clamp circuit. This means that the SYNC_IN timing
for HD signals is different than the timing for SD or PS sig-
nals. For HD signals, the SYNC_IN signal must be high
when the clamp must be active. This is during the time
immediately after the sync pulse while the signal is at the
blanking level. This operation is shown in Figure 3. Note that
the following diagrams indicate output voltage levels for
both 0dB and 6dB gain (1V_pp and 2V_pp video signals at the
FMS6407 output pin).
0dB Gain 6dB
1250mV 2250mV
850mV 1450mV
550mV 850mV
250mV 250mV
0mV 0mV
True Sync Position
Allowable SYNC_IN
Av = 1 (0dB) or 2 (6dB)
0H A_v*700mV
Active
Video
Av*300mV
Av*300mV
Required Sync Tip
Offset (Next Sync Tip
Will Be Offset Correctly)
T1
T2
Sync Timing
Normally, the FMS6407 will respond to bi-level sync and
clamp the sync tip during period ‘B’ in Figure 4(a). When
the filters are switched to high definition mode (30MHz) the
sync processing will respond to tri-level sync and clamp to
the blanking level during period ‘C’ in Figure 4(b).
(a) 2250mV
480i and 480p
850mV
250mV
AB
C
(b) 2250mV
1450mV
850mV
250mV
720p and 1080i
AB B
C
Figure 4. Sync Timing; Bi-Level (a), Tri-Level (b)
The tri-level sync pulse is located such that the broad pulses
in the vertical interval do not trigger the clamp. In order to
improve the system settling at turn-on, the broad pulses will
be clamped to just above ground. Once the broad pulses (and
tri-level sync tips) are above ground, the normal clamping
process takes over and clamps to the blanking level during
period ‘C’ in Figure 4(b).
The FMS6407 is designed to support the video standards
and associated sync timings shown in Table I on page 12
(additional standards such as 483p59.94 will also work
correctly). The filter settings table from page 9 is repeated on
page 12 for convenience.
Figure 3. Tri-Level Blanking Clamp
NOTE: Tri-level sync may only be compressed 5%. If
tri-level sync is compressed more than 5% it may not be
properly located.
REV. 1I July 2005
11