FDMF6704_09 Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – The Xtra Small, High Performance, High Frequency DrMOS Module

Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 24 for power loss testing method. Power loss
calculation are as follows:
(a) P_IN
= (V_IN x I_IN) + (V_5V x I_5V) (W)
(b) P_SW
= V_SW x I_OUT
(W)
(c) P_OUT
= V_OUT x I_OUT
(W)
(d) P_{LOSS_MODULE} = P_IN - P_SW
(W)
(e) P_{LOSS_BOARD} = P_IN - P_OUT
(W)
(f) EFF_MODULE = 100 x P_SW/P_IN
(%)
(g) EFF_BOARD
= 100 x P_OUT/P_IN
(%)
PCB Layout Guideline
Figure 25 shows a proper layout example of FDMF6704 and
critical parts. All of high current flow path, such as VIN, VSWH,
V_OUT and GND copper, should be short and wide for better and
stable current flow, heat radiation and system performance.
Following is a guideline which the PCB designer should
consider:
1. Input ceramic bypass capacitors must be close to VIN and
PGND pin of FDMF6704 to help reduce the input current ripple
component induced by switching operation.
2. The VSWH copper trace serves two purposes. In addition to
being the high frequency current path from the DrMOS package
to the output inductor, it also serves as heatsink for the lower
FET in the DrMOS package. The trace should be short and wide
enough to present a low impedance path for the high frequency,
high current flow between the DrMOS and inductor in order to
minimize losses and temperature rise. Please note that the
VSWH node is a high voltage and high frequency switching
node with high noise potential. Care should be taken to
minimize coupling to adjacent traces. Additionally, since this
copper trace also acts as heatsink for the lower FET, tradeoff
must be made to use the largest area possible to improve
DrMOS cooling while maintaining acceptable noise emission.
3. Output inductor location should be as close as possible to the
FDMF6704 for lower power loss due to copper trace. Care
should be taken so that inductor dissipation does not heat the
DrMOS.
4. The PowerTrench^® 5 MOSFETs used in the output stage are
very effective at minimizing ringing. In most cases, no snubber
will be required. If a snubber is used, it should be placed near
the FDMF6704. The resistor and capacitor need to be of proper
size for the power dissipation.
5. Place ceramic bypass capacitor and BOOT capacitor as
close as possible to the VCIN and BOOT pins of the
FDMF6704 to ensure clean and stable power. Routing width
and length should be considered as well.
6. Include a trace from PHASE to VSWH in order to improve
noise margin. Keep trace as short as possible.
7. The layout should include the option to insert a small value
series boot resistor between boot cap and BOOT pin. The boot
loop size, including R_BOOT and C_BOOT, should be as small as
possible. The boot resistor is normally not required, but is
effective at improving noise operating margin in multi phase
designs that may have noise issues due to ground bounce and
high negative VSWH ringing. The VIN and PGND pins handle
large current transients with frequency components above
100 MHz. If possible, these package pins should be connected
directly to the VIN and board GND planes. The use of thermal
relief traces in series with these pins is discouraged since this
will add inductance to the power path. This added inductance in
series with the PGND pin will degrade system noise immunity
by increasing negative VSWH ringing.
8. CGND pad and PGND pins should be connected by plane
GND copper with multiple vias for stable grounding. Poor
grounding can create a noise transient offset voltage level
between CGND and PGND. This could lead to fault operation of
gate driver and MOSFET.
9. Ringing at the BOOT pin is most effectively controlled by
close placement of the boot capacitor. Do not add an additional
BOOT to PGND capacitor. This may lead to excess current flow
through the BOOT diode.
10. SMOD#, DISB# and PWM pins don’t have internal pull up or
pull down resistors. They should not be left floating. These pins
should not have any noise filter caps.
11. Use multiple vias on each copper area to interconnect top,
inner and bottom layers to help smooth current flow and heat
conduction. Vias should be relatively large and of reasonable
inductance. Critical high frequency components such as R_BOOT,
C_BOOT, the RC snubber and bypass caps should be located
close to the DrMOS module and on the same side of the PCB
as the module. If not feasible, they should be connected from
the backside via a network of low inductance vias.
V_5V
A ^I5V
C_VDRV
DISB#
PWM Input
SMOD#
VDRV VCIN VIN
DISB#
BOOT
PWM
SMOD#
PHASE
VSWH
CGND PGND
I_{IN A}
C_VIN
R_BOOT
C_BOOT
L_OUT
V V_SW
V_IN
I_{OUT A}
C_OUT
V_OUT
Figure 24. Power Loss Measurement Block Diagram
FDMF6704 Rev. G
11
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