CD4046BC Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – Micropower Phase-Locked Loop

Design Information
This information is a guide for approximating the value of
external components for the CD4046B in a phase-locked-
loop system. The selected external components must be
within the following ranges: R1, R2 ≥ 10 kΩ, R_S ≥ 10 kΩ,
C1 ≥ 50 pF.
In addition to the given design information, refer to Figure
5, Figure 6, Figure 7 for R1, R2 and C1 component selec-
tions.
Characteristics
VCO Frequency
Using Phase Comparator I
VCO Without Offset
VCO With Offset
R2 = ∞
Using Phase Comparator II
VCO Without Offset
VCO With Offset
R2 = ∞
For No Signal Input
Frequency Lock
Range, 2 f_L
Frequency Capture
Range, 2 f_C
VCO in PLL system will adjust
VCO in PLL system will adjust to
to center frequency, f_o
lowest operating frequency, f_min
2 f_L = full VCO frequency range
2 f_L = f_max − f_min
Loop Filter Component
Selection
For 2 f_C, see Ref.
Phase Angle Between
Single and Comparator
Locks on Harmonics
of Center Frequency
Signal Input Noise
Rejection
90° at center frequency (f_o), approximating
0° and 180° at ends of lock range (2 f_L)
Yes
High
f_C = f_L
Always 0° in lock
No
Low
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