AN-9005 Datasheet, PDF (10/13 Pages) Fairchild Semiconductor – Driving and Layout Design for Fast Switching Super-Junction MOSFETs

AN-9005
L _GateBond
L_lead
~ 10- 20nH
L _SourceBond
APPLICATION NOTE
Oscillation Circuits
Figure 41 shows observed oscillation waveforms in a PFC
circuit during turn-off transient of a super-junction
MOSFET. In such a case, increasing gate resistance
dampens down the peak drain-source voltage and prevents
gate oscillation caused by lead inductance and parasitic
capacitances of the super-junction MOSFET.
Figure 39. Several Parasitics in TO-220 Package
The impact of the package on performance is limited due to
the fact that the internal gate and source bonding wire
length are fixed. Only the length of the lead can be changed
to reduce the source inductance of the package. Typical
lead inductance of 10 nH, as shown in Figure 40, doesn’t
look like much, but a turn-off a current with
di/dt=500 A / µs is easily possible with these MOSFETs.
The voltage across this inductance is V_IND = 5 V and, with a
turn-off di/dt of 1000 A / µs, the induced voltage is V_IND =
10 V. This short calculation shows that the complete source
inductance, not only the lead inductance of the package,
must be reduced to acceptable value. Low-inductance shunt
resistors are mandatory.
Another source of noise is layout parasitic. Two types are
visible: parasitic inductance and parasitic capacitance. Both
parasitics influence the performance of the layout. As
mentioned before, 1 cm of trace pitch has an inductance of
6-10 nH, which can be reduced by adding one layer on the
topside of the PCB and a GND plane on the bottom side of
the PCB. The other type is the parasitic capacitances. Figure
40 shows the principles of capacitive layout parasitics. The
capacitance between one trace is immediately over the other
trace or GND plane on the other side of the PCB. The
second one is the capacitance built up between the device
and the GND plane. Two parallel traces on both sides of
PCB increase capacitance, but also reduce the inductance of
the loop, resulting in less magnetic noise radiation.
Output inductance
Output capacitance
Switch Node
Vout
GND
PCB Material
GND
GND
Paracitic capacitances
Figure 40. Capacitive Layout Parasitics
Figure 41. Capacitive Layout Parasitics
From a general perspective, there are several oscillation
circuits that affect the switching behavior of the MOSFET,
including internal and external oscillation circuits. Figure
42 shows a simplified schematic of a PFC circuit with both
internal parasitics of a power MOSFET and an external
oscillation circuits given by the external couple capacitance
C_{gd_ext.} of the board layout. Parasitic components in the
devices and boards involve switching characteristics more
as the switching speed is increased. In Figure 42; L, C_o, and
D_boost are the inductor, output capacitor, and boost diode.
C_gs, C_{gd_int}, and C_ds are parasitic capacitances of the power
MOSFET. L_d1, L_s1, L_g1 are the drain, source, and gate wire
bonding and lead inductances of the power MOSFET. R_{g_int}
and R_{g_ext} are the internal gate resistors and the external gate
driving resistors. C_{gd_ext.} is the parasitic gate-drain
capacitance. L_D, L_S, and L_G are the drain, source, and gate
copper trace stray inductances of the printed circuit board.
Gate parasitic oscillation occurs in a resonant circuit by
gate-drain capacitance, C_gd, and gate lead inductance, L_g1,
when the MOSFET is turned on and off. When the
resonance condition (ωL = 1/ωC) occurs, an oscillation
voltage much larger than drive voltage V_gs(in) is generated in
V_gs between the gate and source because the voltage
oscillation due to resonance changes in proportion to the
selectivity Q(=ωL/R = 1/ωCR) of the resonant circuit in
Figure 43. The voltages across the capacitor and inductor,
V_C and V_L, are given by Equations (2) and (3):
V_c

1
2 fC

1
CR

Q V
(2)
V_L
 1 2
fL

V
CL
R

Q V
(3)
where
Q

L
R

1
CR
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/26/14
10
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