AN-9005 Datasheet, PDF (1/13 Pages) Fairchild Semiconductor – Driving and Layout Design for Fast Switching Super-Junction MOSFETs

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AN-9005
Driving and Layout Design for Fast Switching
Super-Junction MOSFETs
Abstract
Power MOSFET technology has been developed towards
higher cell density for lower on-resistance. There are,
however, silicon limits for significant reduction in the on-
resistance with the conventional planar MOSFET
technology because of its exponential increase in on-
resistance according to the increase of blocking capability.
One of efforts to overcome the silicon limit is super-
junction technology in high-voltage power MOSFETs. The
super-junction technology can dramatically reduce both on-
resistance and parasitic capacitances, which usually are in
trade-off. With smaller parasitic capacitances, the super-
junction MOSFETs have extremely fast switching
characteristics and reduced switching losses. Naturally, this
switching behavior occurs with greater dv/dt and di/dt that
affect switching performance via parasitic components in
devices and printed circuit board. It is also related to EMI
performance of the system. Therefore, an optimized design
is very important to operate high-speed MOSFETs. The
purpose of this application note is to discuss driving
methods and layout requirements in relation to switching
performance of fast switching MOSFETs.
Introduction
The power losses of the switching device can be broken
into four parts: conduction losses, switching losses, turn-off
state losses due to leakage current, and driving losses. In
most switching power applications utilizing high-voltage
switching devices, the last two parts can be neglected. The
conduction losses can be reduced through realizing lowest
possible on-resistance. The switching losses are determined
by the duration of switching transient, a period where
current and voltage present simultaneously across the
channel of the device. Faster switching transients reduces
switching power losses. The switching device should have
very low parasitic capacitances to be switched quickly.
Therefore, considerable work has focused on improving on-
resistance and capacitances. Successive generations of
super-junction MOSFET technology have shown dramatic
decrease of the transistor specific on-resistance (R_ON,sp)^[1]-[2].
Smaller die size and faster switching performance can be
achieved by lowering R_DS(ON) and gate charge (Q_G).
However, sharp transitions in voltage and current result in
high-frequency noises and radiated EMI. To achieve low
noise radiation, high values of parasitic capacitances are
required. There is direct conflict in parasitic capacitance
requirements. Based on recent system trends, improving
efficiency is a critical goal and going with slow switching
device just for EMI is not an optimized solution. This note
tackles how to achieve balance between these considerations
when designing with fast-switching power devices.
Super-Junction MOSFET
Technologies
The R_DS(ON) × Q_G, Figure Of Merit (FOM) is generally
considered the single most important indicator of MOSFET
performance in Switching Mode Power Supplies (SMPS).
Therefore, several new technologies have been developed
to improve the R_DS(ON) × Q_G FOM. The super-junction
device utilizing charge balance theory was introduced to the
semiconductor industry ten years back and it set a new
benchmark in the high-voltage power MOSFET market^[3].
Figure 1 shows the vertical structure and electric field
profile of a planar MOSFET and super-junction MOSFET.
Breakdown voltage of a planar MOSFET is determined by
drift doping and its thickness. The slope of electric field
distribution is proportional to drift doping. Therefore, thick
and lightly-doped EPI is needed to support higher
breakdown voltage. The major contribution to on-resistance
of high-voltage MOSFET comes from the drift region.
Therefore, the on-resistance exponentially increases with
the light doping and thick drift layer for higher breakdown
voltage, as shown in Figure 2.
Super-junction technology has deep P-type pillar-like
structure in the body in contrast to the well-like structure of
conventional planar technology. The effect of the pillars is
to confine the electric field in the lightly doped EPI region.
Thanks to this P-type pillar, the resistance of N-type EPI
can be reduced dramatically compared to the conventional
planar technology, while maintaining same level of
breakdown voltage. Therefore, this new technology broke
silicon limit in terms of on-resistance and achieved only
one-third the specific on-resistance per unit area compared
to planar processes^[4]. It is well known that this technology
also achieved unique non-linear parasitic capacitance
characteristics and enabled reduced switching power losses.
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/26/14
www.fairchildsemi.com