SCAN18541T Datasheet, PDF (1/11 Pages) National Semiconductor (TI) – Non-Inverting Line Driver with TRI-STATE Outputs

October 1991
Revised April 2000
SCAN18541T
Non-Inverting Line Driver with 3-STATE Outputs
General Description
The SCAN18541T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control sig-
nals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
Features
s IEEE 1149.1 (JTAG) Compliant
s Dual output enable signals per byte
s 3-STATE outputs for bus-oriented applications
s 9-bit data busses for parity applications
s Reduced-swing outputs source 32 mA/sink 64 mA
s Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
s TTL compatible inputs
s 25 mil pitch SSOP (Shrink Small Outline Package)
s Includes CLAMP and HIGHZ instructions
s Member of Fairchild’s SCAN Products
Ordering Code:
Order Number Package Number
Package Description
SCAN18541TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Names
Pin Names
Description
AI_(0–8)
BI_(0–8)
AOE₁, AOE₂
BOE₁, BOE₂
AO_(0–8)
AO_(0–8)
Input Pins, A Side
Input Pins, B Side
3-STATE Output Enable Input Pins,
3-STATE Output Enable Input Pins,
Output Pins, A Side
Output Pins, B Side
A Side
B Side
Truth Tables
AOE₁
L
H
X
L
Inputs
AOE₂
L
X
H
L
AI_(0–8)
H
X
X
L
AO_(0–8)
H
Z
Z
L
Inputs
BOE₁
BOE₂
BI_(0–8)
L
L
H
H
X
X
X
H
X
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
BO_(0–8)
H
Z
Z
L
© 2000 Fairchild Semiconductor Corporation DS010965
www.fairchildsemi.com