FDP6035L Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

April 1998
FDP6035L/FDB6035L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as DC/DC converters and
high efficiency switching circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
Features
58 A, 30 V. RR_{DDSS(O(ONN) )}==00.0.01119ΩΩ@@VV_GGSS==140.5VV_.
Low gate charge (typical 34 nC).
Low Crss (typical 175 pF).
Fast switching speed.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol Parameter
FDP6035L
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJC
Thermal Resistance, Junction-to-Case
R_θJA
Thermal Resistance, Junction-to-Ambient
© 1998 Fairchild Semiconductor Corporation
30
±20
58
175
75
0.5
-65 to 175
FDB6035L
2
62.5
Units
V
V
A
W
W/°C
°C
°C/W
°C/W
FDP6035L Rev.B