74LCX16841 Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

October 1995
Revised April 2001
74LCX16841
Low Voltage 20-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
General Description
The LCX16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX16841 is designed for low voltage (2.5V or 3.3V)
V_CC applications with capability of interfacing to a 5V signal
environment.
The LCX16841 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V V_CC specifications provided
s 5.5 ns t_PD max (V_CC = 3.3V), 20 µA I_CC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (V_CC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V_CC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16841MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LCX16841MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE_n
LE_n
D₀–D₁₉
O₀–O₁₉
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS012578
www.fairchildsemi.com