100ELT23 Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – 5V Dual Differential PECL to TTL Translator (Preliminary)

Preliminary
September 2002
Revised September 2002
100ELT23
5V Dual Differential PECL to TTL Translator (Preliminary)
General Description
The 100ELT23 is a dual differential PECL to TTL translator
operating from a single +5V supply.
The dual gate design of the 100ELT23 makes it ideal for
applications which require the translation of a clock and a
data signal.
The 100 series is temperature compensated.
Features
s Typical propagation delay of 3.5 ns
s TTL output drive: I_OH = 24 mA; I_OL = −3 mA
s Flow through pinout
s Q Output will default to a LOW with the inputs left Open
s Internal pull-down resistors on inputs
s Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
s Typical I_CCH of 23 mA, I_CCL of 26 mA
s Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
s Moisture Sensitivity Level TBD
s ESD Performance:
Human Body Model > TBD
Machine Model > TBD
Ordering Code:
Product
Order Number Package Code
Package Description
Number Top Mark
100ELT23M
M08A KLT23 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100ELT23M8
(Preliminary)
MA08D KT23 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Top View
Pin Descriptions
Pin Name
D₀, D₀, D₁, D₁
Q₀, Q₁
V_CC
GND
Description
PECL Differential Inputs
TTL Outputs
Positive Supply
Ground
© 2002 Fairchild Semiconductor Corporation DS500774
www.fairchildsemi.com