FAN6754_09 Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – Highly Integrated Green- Mode PWM Controller

Functional Description
Startup Current
Gate Output / Soft Driving
For startup, the HV pin is connected to the line input
through an external diode and resistor; RHV, (1N4007 /
150KΩ recommended). Peak startup current drawn
from the HV pin is (VAC× 2 ) / RHV and charges the
hold-up capacitor through the diode and resistor. When
the VDD capacitor level reaches VDD-ON, the startup
current switches off. At this moment, the VDD capacitor
only supplies the FAN6754 to keep the VDD until the
auxiliary winding of the main transformer provides the
operating current.
Operating Current
Operating current is around 1.7mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
13V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Slope Compensation
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference.
Once VFB is lower than the threshold voltage (VFB-N),
switching frequency is continuously decreased to the
minimum green-mode frequency of around 22KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP = (VFB–0.6)/4, the switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.46V for low-line output power limit.
Leading-Edge Blanking (LEB)
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6754 inserts a synchronized, positive-going, ramp
at every switching cycle.
Constant Output Power Limit
When the SENSE voltage across sense resistor RSENSE
reaches the threshold voltage, around 0.46V for low-line
condition, the output GATE drive is turned off after a
small delay, tPD. This delay introduces an additional
current proportional to tPD • VIN / LP. Since the delay is
nearly constant regardless of the input voltage VIN,
higher input voltage results in a larger additional current
and the output power limit is higher than under low input
line voltage. To compensate this variation for a wide AC
input range, a power-limiter is controlled by the HV pin
to solve the unequal power-limit problem. The power
limiter is fed to the inverting input of the current limiting
comparator. This results in a lower current limit at high-
line inputs than at low-line inputs.
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
Brownout and Constant Power Limited by
HV Pin
blanking time is built in. During this blanking period, the Unlike previous PWM controllers, FAN6754’s HV pin
current-limit comparator is disabled and cannot switch can detect the AC line voltage brownout function and
off the gate driver.
adjust the current limit level. Using a fast diode and
startup resistor to sample the AC line voltage, the peak
Under-Voltage Lockout (UVLO)
value refreshes and is stored in a register at each
sampling cycle. When internal update time is met, this
The turn-on and turn-off thresholds are fixed internally _{peak value is used for brownout and current-limit level}
at 16.5V and 9V, respectively. During startup, the hold- _{judgment. Equation 1 and 2 calculate the level of}
up capacitor must be charged to 16.5V through the _{brownin or brownout converted to RMS value. For}
startup resistor to enable the IC. The hold-up capacitor _{power saving, FAN6754 enlarges the sampling cycle to}
continues to supply VDD until the energy can be _{lower the power loss from HV sampling at light load}
delivered from auxiliary winding of the main transformer. _condition.
VDD must not drop below 9V during startup. This UVLO
hysteresis window ensures that hold-up capacitor
adequate to supply VDD during startup.
is
V_AC-ON (RMS)
=(
0.9V
×
(R_HV +1.6) _{) /}
1.6
2
(1)
V_AC-OFF (RMS)=(
0.81V ×
(R_HV +1.6) _{) /}
1.6
2
; the unit of R_HV is kΩ
(2)
© 2009 Fairchild Semiconductor Corporation
FAN6754 • Rev. 1.0.1
11
www.fairchildsemi.com