XR16L2550 Datasheet, PDF (9/45 Pages) Exar Corporation – LOW VOLTAGE DUART WITH 16-BYTE FIFO

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REV. 1.0.0
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
INTA/B Pin
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
2.8 Crystal Oscillator or External Clock Input
The L2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R2
500 ΚΩ − 1 ΜΩ
R1
0-120 Ω
(Optional)
C1
22-47 pF
1.8432 MHz
Y1
to
24 MHz
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
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